--ROM
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
port(addr:in std_logic_vector(3 downto 0);
clock:in std_logic;
dout:out std_logic_vector(7 downto 0));
end rom;
architecture beh123 of rom is
type rom_arr is array(0 to 15)of std_logic_vector(7 downto 0);
constant mem:rom_arr:=
( "UUUUUUUU","UUUUUUUU","10100010","UUUUUUUU","UUUUUUUU","UUUUUUUU","00000110","UUUUUUUU","01001000","01001001","UUUUUUUU","00101011","UUUUUUUU","UUUUUUUU","UUUUUUUU","UUUUUUUU");
begin
process(clock)
begin
if (clock'event and clock='1') then
dout<=mem(conv_integer(addr));
end if;
end process;
end beh123;