warning while running the simulation

[goodpranoy]

i've written some codes in VHDL.
i am able to compile it, but during simulation the following warning occurs and i cannot get the desired results.

** Warning: (vsim-3473) Component instance "clk : clock_div" is not bound.
plz help.

--top module

library ieee;
    use ieee.std_logic_1164.all;
    
    entity pc_rom_ent is
        port(clock:in std_logic;
            dout:out std_logic_vector(7 downto 0)
            );
        end pc_rom_ent;
        
        architecture pc_rom_arch of pc_rom_ent is
            signal pc_out:std_logic_vector(3 downto 0);
            signal rom_out:std_logic_vector(7 downto 0);
            signal clock_signal:std_logic;
            
            component programcounter 
        port(clock:in std_logic;           
            output:out std_logic_vector(3 downto 0)
            );
        end component;
        
        component rom 
         port(addr:in std_logic_vector(3 downto 0);
         clock:in std_logic;
         dout:out std_logic_vector(7 downto 0)
         );
         end component;
         
         component clock_div 
         port ( CLKin: in std_logic;
              CLKout: out std_logic
          );
          end component;
         
         component instruction_register
        port(data_in:in std_logic_vector(7 downto 0);
        clock:in std_logic;
        data_out:out std_logic_vector(7 downto 0));
    end component;
         
         begin
             
             clk:clock_div
             port map(CLKin=>clock,
                 CLKout=>clock_signal
                 );
             
         ir:instruction_register
         port map( data_in=> rom_out,
         clock=>clock_signal,
         data_out=>dout
         );   
         
         pc:programcounter
         port map(
             clock=>clock_signal,
             output=>pc_out
             );
             
             mem:rom
             port map(
                 addr=>pc_out,
                 clock=>clock_signal,
                 dout=>rom_out
                 );
                 
             end pc_rom_arch;

--clock divider

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock_div is
   port ( CLKin: in std_logic;
          CLKout: out std_logic
          );
end clock_div;
architecture arch of clock_div is

  signal counter: integer:=1;
  signal temp : std_logic := '1';
begin
process(CLKin,counter)
begin
   --if(reset='0') then counter<=0; temp<='1';
    --els
    if(CLKin'event and CLKin='1') then counter <=counter+1;
     if (counter = 1) then temp <= NOT temp; counter<=0;
     end if;
    end if;
   CLKout <= temp;
end process;
end arch;

--instruction register

library ieee;
    use ieee.std_logic_1164.all;
    
    entity instruction_register is
        port(data_in:in std_logic_vector(7 downto 0);
        clock:in std_logic;
        data_out:out std_logic_vector(7 downto 0));
    end instruction_register;
    
    architecture ir of instruction_register is
        begin
            process(clock)
                
                  begin
                      data_out<="ZZZZZZZZ";
                  
-- +ive edge triggered --
                  if(clock = '1') and (clock'event) then
                  
                  data_out <= data_in ;
                
                  
-- for async reset --
                  else
                  data_out <= (others => 'Z') ;
                  end if;
              
                  end process;
                  end ir ;

--ROM

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rom is
port(addr:in std_logic_vector(3 downto 0);
clock:in std_logic;
dout:out std_logic_vector(7 downto 0));
end rom;

architecture beh123 of rom is
type rom_arr is array(0 to 15)of std_logic_vector(7 downto 0);
constant mem:rom_arr:=
( "UUUUUUUU","UUUUUUUU","10100010","UUUUUUUU","UUUUUUUU","UUUUUUUU","00000110","UUUUUUUU","01001000","01001001","UUUUUUUU","00101011","UUUUUUUU","UUUUUUUU","UUUUUUUU","UUUUUUUU");
begin
process(clock)
begin
if (clock'event and clock='1') then
dout<=mem(conv_integer(addr));
end if;
end process;
end beh123;

--program counter

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    
    entity programcounter is
        port(clock:in std_logic;
            
            output:out std_logic_vector(3 downto 0)
            );
        end programcounter;
            
            architecture pc_arch of programcounter is                                  
                begin
                    process(clock)
                        variable pc_int:std_logic_vector(3 downto 0):="0000";
                        begin
                            
                              if clock'event and clock='1' then
                                    pc_int:=(pc_int+1);     
                                    end if;
                                    output<=pc_int;
                                end process;
                            end pc_arch;

 

[TrickyDicky]

This usually means you havent compiled the clk_div entity.

Btw, dividing the clock like this is not recommended on an FPGA.

 

[goodpranoy]

Btw, dividing the clock like this is not recommended on an FPGA.

sir, then what should i do to get a clock with half the freguency of my actual clock?

 

[TrickyDicky]

Use clock enables, not an actual clock.

 

[goodpranoy]

Use clock enables

sir,
i am new to VHDL. so could you explain what a clock enable is with an example?

 

[TrickyDicky]

A clock enable only enables the register when the enable signal is high. A DFFE if you like.

the code would be:

process(clk)
begin
  if rising_edge(clk) then
    if en = '1' then
      --do something when enable is high only
    end if;
  end if;
end process;

Then just create an enable that toggles every clock and then this circuit (above) will only do something every other clock.

Generating your own clocks can cause all sorts of skew problems.

 

[goodpranoy]

thank u sir :smile: