library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ghj is
port(clk,rst:in std_logic;
bw:in std_logic ;
-- a:out std_logic ;
-- test:out integer range 0 to 105;
g:out std_logic_vector(6 downto 0);
-- testrma,outrma:out std_logic_vector(4 downto 0);
rma:in std_logic_vector(4 downto 0);
wrmap,rcvrmap:out std_logic;
wr:out std_logic
);
end;
architecture detect of ghj is
-- type im1x is array(0 to 63) of std_logic ;
-- type im2x is array (0 to 58)of im1x;
type im3x is array(0 to 103) of integer range 0 to 64 ;
type im4x is array (0 to 98)of im3x;
-- type im5x is array (0 to 40)of integer range 0 to 20;
-- type im6x is array (0 to 40)of im5x;
-- signal rmap:im6x;
signal hough:im4x;
-- signal im:im2x;
type vec1x is array (0 to 160) of integer range 0 to 64;--mishe 200 ya kamtar gereft hadaqal 151
signal edgx,edgy:vec1x;
type vec2x is array (0 to 2)of integer range 0 to 105;
signal circlec,circlex,circley,circler:vec2x;
type vec3x is array (0 to 111)of integer range 0 to 41;
type vec4x is array (0 to 115)of integer range 0 to 41;
signal R18x,R18y,R20x,R20y:vec3x;
signal R19x,R19y:vec4x;
-- type vec2x is array (0 to 68) of integer range 0 to 40;
--signal rmapx,rmapy:vec2x;
type state_machine is(s1_rcv,s2_write, s4_rcvrmap,
s6_start,s7_findr,s8_index,
s9_chek,s10_R18,s12_R20,s11_R19,s15,s16);
signal wr1,wr2:std_logic:='1';
signal state:state_machine:=s1_rcv;
signal rmapx,rmapy:integer range 0 to 41:=0;
signal p:integer range 0 to 104;
signal h:std_logic_vector(6 downto 0);
-- signal Rrow:integer range 0 to 3:=0;
begin
process(clk)
variable Rrow:integer range 0 to 3:=0;
variable row,indexx:integer range 0 to 99:=0;
variable clm,indexy:integer range 0 to 104:=0;
variable i,counter:integer range 0 to 160:=0;
variable R:integer range 17 to 21:=17;
variable k,v,j:integer range 0 to 125:=0;
begin
if (clk'event and clk='1') then
if(rst='1')then
if(state=s1_rcv) then
if(clm>63) then
clm:=0;
row:=row+1;
end if;
if(row<59) then
--im(row)(clm)<=bw;
if(bw='1') then
edgx(i)<=row;
edgy(i)<=clm;
i:=i+1;
end if;
-- sum <=bw;
clm:=clm+1;
else
state<=s4_rcvrmap;
clm:=0;
row:=0;
rcvrmap<='1';
end if;
elsif(state=s4_rcvrmap)then
if(clm>40) then
clm:=0;
row:=row+1;
end if;
if(row<41) then
if(rma="10010")then
R18x(j)<=Row;
R18y(j)<=clm;
j:=j+1;
end if;
if(rma="10011")then
R19x(k)<=Row;
R19y(k)<=clm;
k:=k+1;
end if;
if(rma="10100")then
R20x(v)<=Row;
R20y(v)<=clm;
v:=v+1;
end if;
clm:=clm+1;
else
state<=s6_start;
clm:=0;
row:=0;
v:=0;
k:=0;
j:=0;
rcvrmap<='0';
wrmap<='1';
end if;
elsif(state=s6_start)then --sefr kardan hough
if(clm>103) then
clm:=0;
row:=row+1;
end if;
if(row<99) then
hough(row)(clm)<=0;
clm:=clm+1;
elsif(R<20)then
R:=R+1;
state<=s7_findr;
clm:=0;
row:=0;
else
state<=s2_write; --kharej shodan az halqe tabdil hough
clm:=0;
row:=0;
Rrow:=0;
end if;
elsif(state=s7_findr)then --peida kardane R haye khas
if(R=18)then
state<=s10_R18;
end if;
if(R=19)then
state<=s11_R19;
end if;
if(R=20)then
state<=s12_R20;
end if;
elsif(state=s10_R18)then
if(j<112)then
rmapx<=R18x(j);
rmapy<=R18y(j);
j:=j+1;
state<=s8_index;
else
j:=0;
state<=s6_start;
end if;
elsif(state=s11_R19)then
if(k<116)then
rmapx<=R19x(k);
rmapy<=R19y(k);
k:=k+1;
state<=s8_index;
else
k:=0;
state<=s6_start;
end if;
elsif(state=s12_R20)then
if(v<112)then
rmapx<=R20x(v);
rmapy<=R20y(v);
v:=v+1;
state<=s8_index;
else
v:=0;
state<=s6_start;
end if;
elsif(state=s8_index)then--ezafe kardan be matris hough
if(counter<i)then--sakht inex
indexx:=edgx(counter)+rmapx-1 ;
indexy:=edgy(counter)+rmapy-1;
hough(indexx)(indexy)<=hough(indexx)(indexy)+1; --ezaf kardan hough marbor be R
counter:=counter+1;
else
state<=S9_chek;
counter:=0;
end if;
elsif(state=s9_chek)then--hazfe meqdarhayi ke az treshhold meqdar kamtari daran
if(clm>103) then
clm:=0;
row:=row+1;
end if;
if(row<99) then
if(hough(row)(clm)>60)then
circlex(Rrow)<=row;
circley(Rrow)<=clm;
circlec(Rrow)<=hough(row)(clm);
circler(Rrow)<=R;
Rrow:=Rrow+1;
end if;
clm:=clm+1;
else
state<=s6_start; --kharej shodan az halqe tabdil hough
clm:=0;
row:=0;
end if;
elsif(state=s2_write)then --write the image in fail txt
p <=circlex(Rrow);
state<=s15;
elsif(state=s15)then
h<=conv_std_logic_vector(p,7);
state<=s16;
elsif(state=s16)then
g<=h;
end if;
else
wr<='0';
end if;
end if;
end process;
end;