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warning in ISE(latches maybe generated from incomplete case or if statements)

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hello,when I compiled the program ,I face with this warning , how can I remove this warning?
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.my_package.all;
entity Find_Min_Values_one_rowis
  port(sum:in int;clk_external,clk,reset:in bit;--L:in matrix1xN;
  out_min_1,out_min_2:in int;index_min:in bit_vector(2 downto 0);sign_value:in matrix1x8sign;
  sign_each_row:in integer range -1 to 1;  H,col_each_rowblock: in matrix1x8;out_min_1_new:out int;out_min_2_new:out int;
  index_min_new:out bit_vector(2 downto 0);sign_value_new:inout matrix1x8sign;sign_each_row_new:out integer range -1 to 1;as:out matrix1x8 ;col:out matrix1x8;ii:out int);
end;
 architecture behave of Find_Min_Values_one_row is
 component MUX_8x1 
  port(sel:in bit_vector(2 downto 0);in1:in matrix1x8;out1:out int);
end component;
component MUX_4x1 
  port(sel:in bit_vector(1 downto 0);in1:in bit_vector(1 to 4);out1:out bit);
end component;
component MUX_2x1 
  port(sel:in bit;in1:in bit_vector(1 to 2);out1:out bit);
end component;
component find_min_2_value 
  port(in1,in2:in int;out1:out int;ca:out bit);
end component;
component find_min_s 
  port(in1,in2:in int;out1:out int);
end component;  
--signal i:int:=1;
signal l:matrix1xn;
signal abs_Mes_v_to_c,Mes_v_to_c:matrix1x8;
signal index:int;
signal flag1:bit_vector(1 to 4);
signal flag2:bit_vector (1 to 2);
signal index_0,index_1,index_2:bit;
signal out1:matrix1x4;
signal out2:matrix1x2;
signal out_s:int;
signal sel_0,sel_4,sel_6:bit_vector(1 downto 0);
signal sel_2,sel_5,sel_7:bit_vector(2 downto 0);
signal a0,a1,a2:int;
signal sel_3,index_a10,index_a11,index_a20:bit;
begin
   with index_min select 
  index<=1 when "000",
  2 when "001",
  3 when "010",
  -4 when "011",
  5 when "100",
  6 when "101",
  7 when "110",
  8 when others;
  
  
process(clk,reset,clk_external)
    variable  i,s,a,c :int:=0;variable b:integer;
    variable col_index_nonzero,out_1,Mes_c_to_v,d,Lnew:int;
    variable multiple_sign,multiple_sign_0,sign_value_i:integer range 1 downto -1;
    begin 
      if reset ='1' then 
        s:=0;i:=0;multiple_sign:=1;
      else
        if (clk 'event and clk='1' )then
          if i=8 then
           i:=1;s:=0;
          else
           i:=i+1;
          end if;
        end if;
        s:=col_each_rowblock(i)+sum-1;
        b:=(col_each_rowblock(i)+sum-1)-H(i);
          if b>0 then 
            a:=1;
          else
            a:=0;
          end if;
        
        case a is 
          when 0 => col_index_nonzero := s;
          when others =>col_index_nonzero:=s-96;
        end case;
        col(i)<=col_index_nonzero;
        if col_index_nonzero=H(i)-96 then 
          col_index_nonzero:=H(i);
        end if;
        if i=index then  
          out_1:=out_min_2;
        else
          out_1:=out_min_1;
        end if;
        Mes_c_to_v:=out_1 * sign_value(i)* sign_each_row ;
        --v<=col_index_nonzero;
        c:=L(col_index_nonzero);
        d:=c-Mes_c_to_v;
        as(i)<=d;
        abs_Mes_v_to_c(i)<=abs(d);
        if d>= 0 then 
	        sign_value_i:=1;
	      else
	        sign_value_i:=-1;
	      end if;
	      multiple_sign_0:=multiple_sign;
	      multiple_sign:=multiple_sign_0*sign_value_i;
	      sign_each_row_new<=multiple_sign;
	      sign_value_new(i)<=sign_value_i;
	      Mes_v_to_c(i)<=d;
        ii<=i;
        
      
      end if;
    end process;  
    Com_10:find_min_2_value port map(abs_Mes_v_to_c(1),abs_Mes_v_to_c(2),out1(1),flag1(1));
    Com_11:find_min_2_value port map(abs_Mes_v_to_c(3),abs_Mes_v_to_c(4),out1(2),flag1(2));
    Com_12:find_min_2_value port map(abs_Mes_v_to_c(5),abs_Mes_v_to_c(6),out1(3),flag1(3));
    out1(4)<=abs_Mes_v_to_c(7);flag1(4)<='0';
    Com_01:find_min_2_value port map(out1(1),out1(2),out2(1),flag2(1));
    Com_02:find_min_2_value port map(out1(3),out1(4),out2(2),flag2(2));
    Com_a :find_min_2_value port map(out2(1),out2(2),out_min_1_new,index_2);
    MUX_index_1 :MUX_2x1 port map(index_2,flag2,index_1);
    sel_0<=index_2 & index_1;
    MUX_index_0:MUX_4x1 port map(sel_0,flag1,index_0);
    index_min_new<=sel_0 & index_0;
    sel_2<=sel_0 & not(index_0);
    MUX_a0:MUX_8x1 port map(sel_2,abs_Mes_v_to_c,a0);
    sel_3<=not index_2;
    MUX_index_all: MUX_2x1 port map(sel_3,flag2,index_a11);
    sel_4<=not index_2 & index_a11;
    MUX_index_a10 :MUX_4x1 port map(sel_4,flag1,index_a10);
    sel_5<=not(index_2) & index_a11 & index_a10;
    MUX_a1:MUX_8x1 port map (sel_5,abs_Mes_v_to_c,a1);
    sel_6<=index_2 & not index_1;
    MUX_index_a20 :MUX_4x1 port map (sel_6,flag1,index_a20);
    sel_7<=index_2 & not index_1 & index_a20;
    MUX_a2 : MUX_8x1 port map (sel_7,abs_Mes_v_to_c,a2);
	 Com_min_s_0: find_min_s port map(a0,a1,out_s);
	 Com_min_s_1:find_min_s port map(out_s,a2,out_min_2_new);

warnings
Code: 
Found 1-bit latch for signal <abs_Mes_v_to_c<1><12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<1><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<2><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<3><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<4><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<5><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<6><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<7><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <abs_Mes_v_to_c<8><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_each_row_new<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_each_row_new<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<1><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<1><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<2><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<2><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<3><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<3><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<4><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<4><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<5><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<5><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<6><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<6><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<7><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<7><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<8><1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <sign_value_new<8><0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1293 - FF/Latch <sign_value_new<1>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<2>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<4>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<3>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<5>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<7>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<6>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<8>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <sign_value_new<2>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<1>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<3>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<4>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<5>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<7>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<6>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sign_value_new<8>_0> has a constant value of 1 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2170 - Unit Find_Min_Values_one_row : the following signal(s) form a combinatorial loop: multiple_sign<1>, Mmult_n2559_Madd2_lut<1>.
WARNING:Xst:2170 - Unit Find_Min_Values_one_row : the following signal(s) form a combinatorial loop: multiple_sign<0>1.
WARNING:Xst:1293 - FF/Latch <i_4> has a constant value of 0 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_5> has a constant value of 0 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_6> has a constant value of 0 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_7> has a constant value of 0 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_8> has a constant value of 0 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_9> has a constant value of 0 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_10> has a constant value of 0 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_11> has a constant value of 0 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_12> has a constant value of 0 in block <Find_Min_Values_one_row>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1336 -  (*) More than 100% of Device resources are used
 

What's this?....Too many variables mixed with signal assignments outside clock, hope you know what you are doing....
Code: 
if col_index_nonzero=H(i)-96 then 
          col_index_nonzero:=H(i);
        end if;

Check this out. It is connected to your net "abs_mes_v_to_c", this does not cover all cases, resulting in latch. Try to cover all cases. Also, your design has too many variables, take special care for timing. It will trouble you at last.

Cheers...
 

I deleted these from the program,but the warning didnt remove.
 

As xtcx suggested, generally ISE complains with cases in which cases (if or case statements) are not covered. Are you sure your "abs_mes_v_to_c" occurs in cases statements that are full covered (e.g., have the others case)? Check also in lower-level component 'find_min_2'.

The same applies for other signals, e.g. signal 'sign_value_new' that appears in the else branch of the 'if d>= 0' statement. Try also check with Xilinx, you can find answers to common synthesis issues in their web-site!

Cheers
 

the issue here is the async reset. notice that the sync portion of the process is very small, and the majority of the process really only defines combinatorial logic. notice that, when rst=0, there is logic defined for the value of these signals. However, when rst=1 there is not a definition for several of these signals. In these cases, the language assumes each of these signals retains its current value, which requires a latch with rst as the clock/gate input.

- - - Updated - - -

the issue here is the async reset. notice that the sync portion of the process is very small, and the majority of the process really only defines combinatorial logic. notice that, when rst=0, there is logic defined for the value of these signals. However, when rst=1 there is not a definition for several of these signals. In these cases, the language assumes each of these signals retains its current value, which requires a latch with rst as the clock/gate input.
 

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