warning - Cpld:310 - Cannot apply TIMESPEC TS1000

[chxgzl4862]

why this warning?

hello !

Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for
analysis.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1000 =
PERIODERIOD_SPIFsmClk.Q:0.000 nS because of one of the following: (a) a
signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.

my program
entity SPI_FSM is
------------------------------------------
port (
SPI_FSM_CLKIN: in std_logic;
SPI_FSM_RST: in std_logic;
SPI_FSM_CS: in std_logic;
SPI_FSM_MOSI: out std_logic;
SPI_FSM_MISO: in std_logic;
SPI_FSM_DATAIN: in std_logic;
SPI_FSM_DATAOUT: out std_logic;
SPI_FSM_DIVNUM: in std_logic_vector ( 7 downto 0 )
);
------------------------------------------
end SPI_FSM;

architecture Behavioral of SPI_FSM is
------------------------------------------
component SPI_CLK
port (
SPI_CLK_CLKIN: in std_logic;
SPI_CLK_RST: in std_logic;
SPI_CLK_CS: in std_logic;
SPI_CLK_OUT: out std_logic;
SPI_CLK_DIVNUM: in std_logic_vector ( 7 downto 0 )
);
end component;
------------------------------------------
------------------------------------------
signal SPIFsmClk: std_logic;
------------------------------------------
begin
------------------------------------------
SPI_FSM_CLK: SPI_CLK
port map (
SPI_CLK_CLKIN => SPI_FSM_CLKIN,
SPI_CLK_RST => SPI_FSM_RST,
SPI_CLK_CS => SPI_FSM_CS,
SPI_CLK_OUT => SPIFsmClk,
SPI_CLK_DIVNUM => SPI_FSM_DIVNUM
);

SPI_FSM_STEP_MOSI:
process ( SPI_FSM_RST,SPI_FSM_CS,SPIFsmClk,SPI_FSM_DATAIN )
begin
if ( SPI_FSM_RST = '0' ) then
SPI_FSM_MOSI <= '1';
elsif ( rising_edge( SPIFsmClk ) ) then
if ( SPI_FSM_CS = '0' ) then
SPI_FSM_MOSI <= SPI_FSM_DATAIN;
else
SPI_FSM_MOSI <= '0';
end if;
end if;
end process SPI_FSM_STEP_MOSI;

SPI_FSM_STEP_MISO:
process ( SPI_FSM_RST,SPI_FSM_CS,SPI_FSM_MISO,SPIFsmClk )
begin
if ( SPI_FSM_RST = '0' ) then
SPI_FSM_DATAOUT <= '0';
elsif ( rising_edge( SPIFsmClk ) ) then
if ( SPI_FSM_CS = '0' ) then
SPI_FSM_DATAOUT <= SPI_FSM_MISO;
else
SPI_FSM_DATAOUT <= '0';
end if;
end if;
end process SPI_FSM_STEP_MISO;
------------------------------------------
end Behavioral;

how can i do with it? thanks!

 

[farhada]

why this warning?

Where is your constraint file, it seems that the problem is located there rather than in your VHDL file.

Best regards,
/Farhad Abdolian