Warning at using memory register [31:0] mem [255:0]

[rajavel.rv]

i could not solve this warning

WARNING:Xst:2999 - Signal 'mem', unconnected in block 'rom_blocks_reverse_shifts', is tied to its initial value.

my coding style is

reg [31:0] mem [255:0];

how can i solve this....

 

[rberek]

We are going to need to see more of your code than this, This line is not the problem. The warning implies that you never use mem, but without seeung the rest of your cide ee cannot say for sure.

r.b.

 

[rajavel.rv]

We are going to need to see more of your code than this, This line is not the problem. The warning implies that you never use mem, but without seeung the rest of your cide ee cannot say for sure.

r.b.

---

Code VHDL - [expand]
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module (
input wire byte_in,
output wire byte_out);
 
reg [7:0] mem [3:0];
 
 
initial begin
 
   mem [0] = 4'b0010;
   mem [1] = 4'b1100;
   ----
 ---
end;
 
assign byte_out = mem[byte_in];
 
end

---

- - - Updated - - -

Here, we are assigning the memory declaration of register(reg) inside of the initial block... i know that is the bug... i need how can i implemented this one without warnings and errors...

 

[rberek]

Well, firstly you have syntax errors. Both byte-in and byte_out are single bit values and should be made to be multi-bit. Byte-in should be 4-bits to address your memory and byte-out should be 8-bits since your memory holds 8-bit values.. And the initial statement is not always synthesizeable so you should avoid using it in RTL. And you have no module name.

You have described a module that immediately, and combinatorially, takes the input data and converts it into other data. The only thing that is actually stored is the conversion value, but because they never change, the synthesizer can just tie them to power or ground and save any register or memory elements. It won't create a ROM since FPGA ROMs require clocks and you have not provided one. FPGA memories need a signal to tell then when to output or store data. THey won't do it continually. If you have no clock, no memory or flipflop storage will be inferred.


You could achieve the same thing with:

module blah (
   input   wire  [4:0]   byte_in,
   output wire  [7:0]   byte_out
);
 
always @ (*) begin
   case(byte_in)

      4'b0000: byte_out = 8'b0000_0010;
      4'b0001: byte_out = 8'b0000_1100;
       ...
  endcase
end

endmodule

r.b.

 

[rajavel.rv]

Actually, this style of coding we are having already "case statement inside of always block"; but its takes more LUT; and its generated as a distributed memory; am need a single_port_block_ram without clk in combination logic ;


am using a always statement means its takes LUT'S ;


Thanks & Regards
Rajavel