Fosc = 12MHz
MSEL bits (00100) -> Value of M = 5
PSEL bits (01) -> Value of P = 2
The above values load into PLL0CFG=0x24
Therefore:
CCLK = 60MHz
Fcco = 240MHz
View attachment 66052
If VPBDIV = 1, then the core clock CCLK = PCLK the peripheral clock.
PCLK = 60MHz
Concerning the following parameters:
MAMCR=0x02; // enables memory accelerator module
MAMTIM=0x04; // configures MAM fetch cycles
You can find additional information relevant to the LPC2148 and PLL configuration in the following documents:
Getting Top Performance from NXP's LPC Processors
Clocking ARM with Crystal oscillator and PLL
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