Want my design to work right the first time!

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3Deye

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Hi,

Just finished a design of a 8-Layer PCB, the highest frequency is 125MHz.

I want this design to work right the first time, how should I revise the design and what should I take care of?

Something like a checklist will be much appreciated

Thanks.
 

This link applies specifically to FPGAs, but there are some general guidlines.

PCB Checklist

Here's another.

**broken link removed**

There's LOTS and LOTS of this information out there if you spend some time searching the web.
 

Have you used signal integrity simulation ?
How many high speed boards have you done before?
What is the layer usage?
Is there DDR memory or high speed ethernet.
Without extensive simulation, you will be lucky if it works first time, very lucky.
There is a lot of info on high speed design on this froum...

I cant think of any complex design I have ever worked on has not had to be modded in 25 years
 

Thanks Barry and marce,
1. Have you used signal integrity simulation ?
2. How many high speed boards have you done before?
3. What is the layer usage?
4. Is there DDR memory or high speed ethernet.
Click to expand...
1. Yes, I did SI analysis and found some violations and solved them all.
2. This is the first high speed board I design, that's why I'm a bit worried
3. Signal - GND - Signal - PWR - GND - Signal - PWR - Signal
4. SDR DRAM only.
 

Apart from what others have already told... make sure of the following...
1. You have taken care of power supply jitters- ensure you bhave chosen proper Ferrite bead and correct number of decoupling caps.
2. Schematics is "logically" correct
3. And most important of all- your design is correct by construction.
 

@cks3976, thanks, I'll give another check for the PDN.
 

Did reply in depth earlier this week, unfortenatly a glitch lost some data...
firstly Good luck.
Two signal layers (one definetly) will use a PWR layer for return currents, if this power layer has splits in it be careful what traces cross the splits.
 

@marce, good point, I think I should concentrate on layer 8 signals since they're all referenced to PWR layer.

After some revision, I found that the generated supplies are referenced to DGND and powering Analog VDD of a DAC chip, I already split the GND plane to AGND and DGND, but the power line is not separated, please check the attached image:


Will this cause any problem? should the +12V line be split using an inductor?
 
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I don't split ground planes into analogue and digital. Most if not all the reading matter regarding this by the people such as Henry Ott, chip manufacturers etc says one contigous ground plane is best.
Analogue supplies are often cleaned up by using a pi filter, cap-ferrite bead-cap, but the ground plane keep as one.
 

Please don't forget that a DAC or ADC is considered an analog circuit. Use moats with filters as marce mentioned is a very good solution.
Or use moats to spearate the GND's and only connected the plane together under the converter.
 

No DONT SPLIT....unless you realy have to, and you realy know what you are doing.... my experience is one contigous plane is best
http://www.hottconsultants.com/pdf_files/june2001pcd_mixedsignal.pdf
Grounding of Mixes Signal Systems
**broken link removed**
An intuitive, practical approach to mixed-signal grounding
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http://focus.ti.com/lit/ml/slyp167/slyp167.pdf
http://www.ieee.org.uk/docs/emc1206a.pdf
**broken link removed**
**broken link removed**
**broken link removed**

Common Mode Ground Currents
 
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