want help for designing low voltage low dropout regulator (LDO)

[yogeshree]

hello

can anyone tell me how to decide input voltage range n reference voltage for designing LDo in 45nm CMOS technology??

 

[erikl]

Input voltage range is (max. permissible voltage for your process) .. (output voltage + dropout voltage).

Reference voltage is anything between about threshold voltage and (output voltage - threshold voltage).

 

[yogeshree]

means input voltage and ouput voltage does not depends on technology

 

[dick_freebird]

The output voltage is set by your "customer" (the load).
Probably no way around that.

The input voltage, you would have to choose from what
is available close-in. Presumably some pervasive resource
and hopefully not that much higher than the output, else
you will not be "low dropout" and not efficient.

Reference must be at or below output voltage (unless
you want to gain up the output, which would be so laggy
that performance / stability would suffer). For very low
output voltages you often see a standard bandgap with
a post-divider (and maybe filter). But for very low input
voltage you need either a sub-bandgap core or to have
an "AUX" supply (common on ULDOs for 1V and under, to
see a 3.3V - 5V VAUX pin). The trick of splitting your
power path and the "housekeeping" supply is helpful.

Technology and application details are not independent,
unless you want to leave something on the table (which
may be a market-share calculation, the relative merits of
a do-all, suboptimal part vs a part highly optimized for a
narrow range of applications). If you only have one, or are
coming to the party after technology decisions are locked
down, then you can quit worrying about that and get on with
dealing.