The problem here is that clocking block inputs are synchronous events with the clocking block event. Instead of the
wait statement use
Code Verilog - [expand] |
1
| @(tif1.cb iff tif1.cb.data) |
My general rule is do not mix clocking block events with any other events or
wait statements.
BTW, another general rule is only use blocking assignments for generating clocks. This is especially important when you are generating multiple clocks that are derivatives of other clocks.