You know, nobody will suggest you a good solution without showing the required specifications, there is a lot. Speed, offset, slew rate, consumption, what and how much will be the load, etc.
But a very important thing, if you want to switch those NMOS transistors in circuit 2 assume the feedback node's voltage will vary a lot, and the resistance of the transistors will change with the varying Vgs.
Use parallel PMOS-NMOS switches (transfer gates) rather to keep the switch resistance at low, use minimum length for them and relatively high widths.
If under control the total switch resistance values always lower like 10 times than the other R values the switches won't cause problem.