you need to use tox(thickness of oxide)
Cox=E0*Er/tox
E0=8.854e-12F/m
Er=3.9 for SiO2
Make sure you use tox in meters to end up with Cox with units F/m^2.
Usually Cox is written as F/(um)^2
You want to use the largest device you can, to drive
down the relative contribution of other capacitances
(W-dependent cgdo, cgso especially, but also the stray
routing and pad parasitics - or you want an equivalent
layout minus the test FET, for de-embed).
Then, you want to drive the gate to its maximum "on"
voltage to minimize series resistance and eliminate the
contribution of series depletion capacitance.