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Voltage spike from output of regulator during startup

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pacman22

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Hey!

I have designed a 4 phase regulator to output 0.85V @100A using LTM4650 and simulated it on LTSpice. During transient analysis, I found that there is a voltage spike till 1.29V and then stabilizes to 0.85V.
This spike can not be tolerated for SoC application. Can you suggest how this spike can be eliminated?

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Hi,

How to
(I've never used this device, never read it's datasheet before)
* open the datasheet
Since your problem is the start behaviour
* do a datasheet search for "start"
... immediately find out that the device has some kind of soft start feature
... go on with search for "start" to find out how to set up the start feature
... (within seconds) find out that the device is specified with Css = 0.01uF
... cross checking your schematic .... shows that you use 0.0000001uF. Why?

--> rectify this, do a new test, report results.

Further search of datasheet shows that they recommend to use an even larger Css of 0.1uF.


Klaus

Added: the above method is for "debugging".
But you (as the designer) need to read the whole datasheet. Maybe not every single word, but at least all section headlines. So you get a fast overview about the device and it's features....and it's design requirements.

Thus, out of curiosity I did a search in "requir" ...
... and (also within one minute) found out that (on page 13) it says that "input capacitors are required).
This is no option, it is mandatory, ....but I miss them on your design.

There may be even more issues.
--> Make the datasheet your friend and read it.

Klaus
 
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there is no soft start to mitigate the effect of error amp wind up at start ....
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0.1pF is not much of a cap .... pacman ...
 
Last edited:

there is no soft start to mitigate the effect of error amp wind up at start ....
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0.1pF is not much of a cap .... pacman ...
Actually there is (if you have your fingers in the guts of the IC). You use the error amp to control the soft start by holding the vref to ref gnd and then allowing it to ramp to true vref level leisurely.

If your SS scheme defeats what the error amp wants to be doing, it'll sit there and pout for a while.

High VIN slew can also make kooky control loop behaviors as different bits get right, in a cascade. Solve this by upstream SS (or build it into your connect switch for VIN?).

Yet another basic problem is, good luck getting a good bandgap with VIN below Vbg. This transition should be covered up by UVLO you would think. Why not?
 

I changed the value of Css to 0.01uF and added input bulk capacitors. Now, I am getting ripples at the output. Is it desirable?
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I tried adding a 10Meg load resistor at the output, there are still ripples at the output.
 

Hi,

I wrote "suitable" ... and I meant it seriously.
You are designing for 100A.
And you think 10M at 0.85V is suitable? worse than 1 : 1billion.

10M is not suitable
10k is not suitable
even 10 Ohms is not suitable, since it draws just 0.085A (still 1 : 1270)

Klaus
 

The "noise" is switching ripple and you can look to output filter and measurement setup, if it needs to be reduced (maybe not, output voltage ripple ought to be somewhere in the design-to specs).

You can tell this by how it abruptly starts in around the UVLO threshold.
 

What you can also do, if you dont want overshoot at start up...is you can pre-charge your output with some other converter, which has the facility to avoid ovrshoot at start up...eg, an external error amplifier where you can add some zeros to error amp , by way of the input Z......and do like that.
 

Klaus is right - you do not state the load in the sim, you will want to see the result at 10A and full power.

Be aware the hardware will behave quite differently to your sim.
 

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