Voltage drop using 1 MOS

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Agrum

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Hello,

I have a question that maybe is very stupid but I'm loosing myself.

I have the DC power supply (Vdd) and I need a DC voltage of Vdd-3V for biasing a device. The current absorbion must be very low. My professor suggestion is to use 1 MOS and its Vgs but I don't understand how. I thought that he meant a mos connected as follow:

- drain to Vdd
- gate to Vdd
- source to the point where i want Vdd-3V

but it doesn't work as expected. Any suggestion?
Thanks
 

Hi,

You mean a MOSFET?
N-channel or P-channel?

Draw a schematic (hand drawn) of your idea.
What does "it doesn't work as expected" exactly mean?
Show us the test setup.
And what is your load?

Klaus
 

Using a MOSFET as a "diode drop" is a pretty poor idea
if you want any decent tolerance. Too much variability.
At very low current you would need a very long and
narrow device to get that much from from a single FET
and it would be all over the place with temperature,
process, current.

I would go for a "poor boy LDO" fed by a resistor
divider, diff pair and source follower NMOS. This can
be pretty stable and repeatable. If you have a ready
voltage reference resource then use an output divider
for feedback.

A quantity for "very low" current consumption would
be helpful to you, in picking a topology and values.
 

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