voltage domain crosing interface(VDCI)

can any one tell me about the timing challenges in VDCI ?

The main challenge would be that differen voltage domains would have different PVT conditions and hence if OCV is considered then even small paths with not so huge transition problems could become potential setup and hold hazards.
Another challenge could be that suppose the launch clock is in better condition (V=1.2) and capture clock is in worst condition (1.0) then the data path would see less delay, clock path would see more and hence data would reach faster than clock, making way for hold vio to occur.

Ro9ty