Volt second imbalance, how it works and what can be done about it.

[Piet de Pad]

Dear reader,
I want a better understanding about flux walking in iron core transformers which are connected to a SPWM MOS FET bridge or half bridge.
I understand that flux walking occurs in transformers if the number of Volt seconds per half cycle of a SPWM signal is not exactly the values of Volt Seconds in the second negative half cycle. I understand this phenomenon but want to understand better the mechanisms to prevent it. My request is to correct me when I'm wrong and confirm when I'm right, and to add your knowledge about this topic when I'm incomplete.

Mosfet RDson:
Flux walking or mismatch in Volt Seconds (VoSe) results in a growing DC current in the windings. This will result in an imbalance in current in the mosfets that drive the positive and negative cycles of the SPWM of the coil. This results is a difference in power loss in these Mosfets and that power loss results in a lost loss of VoSe in the coil with the highest MOSFET loss. If the difference in VoSe is absorbed by the loss in the MOSFET a DC current will run in the coil but after time the flux walks come to a stand still. The secondary side of the transformer will make an AC signal.
To compensate in this way for VoSe the mosfet's MUST NOT be Thermal coupled on one heat sink but need to be place on individual separated heat sinks. The mosfets' should not have a too low RDSon.
Question is this statement correct?

Non linear BH curve.
In case flux walking happens and it will, it will follow the BH curve which is not linear at around 1.2T for silicon steel. The flux walk stops at a point where the difference in VoSe is compensated by the decrease in magnetization, that is were the saturations starts.
Here it becomes slippery for me and I would like to have a better understanding. This is what I think, the design of the transformers is done just below the saturation field strength in Oested or A/m. A DC current that occurs because of a flux walk will Push the magnetic field into saturation and therefor result in a loss of VoSe and balance it. The non linearity of the magnetic materials works as negative feedback on the VoSe balance error. The transformer should be designed with just enough windings that make it work below the saturation point. When VoSe errors happens the saturation with deal with the elimination of the imbalance of it.
Question is this statement correct?

Magnetization and load Current waveform.
To measure the current in the (half) Hbridge a small resistor and a current to voltage amplifier can be used. Assuming I want to measure the current with a micro controller it's handy to know what the shape is of that current. Given the fact that the Coil is activated with a SPWM signal I expect to see a small magnetization sine wave current and added on it a load current. Since the Magnetization current is a Sine wave the lead current is a sine wave too. Who looks in detail will see a small saw wave superimposed on this sine wave load current.
Question is this statement correct?

Volt*Second Control.
SPWM is generated using a sine wave table. Mathematical only one quarter, one quadrant of sine wave values are necessary to construct one period of a SPWM Sine wave. SPWM is generated using a timer in a controller. The values of the Sine table should be chosen in a way that the timer interrupt routine can use an up down counter to read the sine wave values to construct one half of a full cycle. The best PWM mode to be used is Center-aligned mode.
Question is this statement correct?

I leave it here for the moment, Hope some one has time and will help.
regards

 

[Easy peasy]

most experienced engineers look at the ( magnetising ) current peaks, and use this information to slightly adjust the PWM strategy to keep the system bounded. - this effectively eliminates the flux walking problem - although the BH loop can move around inside these peaks.

 

[BradtheRad]

I think a solution is in the push-pull arrangement of two stacked capacitors. Their join automatically adopts 1/2 of supply voltage. The volt level rises and falls slightly during a cycle, accommodating lopsided current and voltage differences. (I believe that's the explanation.)
The transformer needs to be constructed with a widerr ratio.

Click the link below to see my animated interactive simulation:

1) Navigates to falstad.comm/circuit
2) Loads my schematic into the simulator
3) Runs it on your computer (Java required).

tinyurl.com/yqg7c78f

 

[Piet de Pad]

most experienced engineers look at the ( magnetising ) current peaks, and use this information to slightly adjust the PWM strategy to keep the system bounded. - this effectively eliminates the flux walking problem - although the BH loop can move around inside these peaks.

Yes I was thinking about that too, but I do want to understand this mechanism in better detail.

--- Updated Oct 14, 2023 ---

I think a solution is in the push-pull arrangement of two stacked capacitors. Their join automatically adopts 1/2 of supply voltage. The volt level rises and falls slightly during a cycle, accommodating lopsided current and voltage differences. (I believe that's the explanation.)
The transformer needs to be constructed with a widerr ratio.

Click the link below to see my animated interactive simulation:

1) Navigates to falstad.comm/circuit
2) Loads my schematic into the simulator
3) Runs it on your computer (Java required).

tinyurl.com/yqg7c78f

View attachment 185405

You need to check that because my information is that the capacitors generate the same problem en don't resolve flux walking

 

[D.A.(Tony)Stewart]

Symmetrical Push-Pull

SMPS: Symmetrical Isolated Converters

Symmetrical Isolated converters use the full available flux swing in both quadrants of the B-H loop, utilizing the core much more effectively

talema.com

Asymmetric or Flyback Push-Clamp

https://www.ednasia.com/how-to-improve-flyback-efficiency-with-a-nondissipative-clamp/

Flux Walking p 4.6

https://www.ti.com/lit/ml/slup126/slup126.pdf

 

[BradtheRad]

my information is that the capacitors generate the same problem en don't resolve flux walking

Your statement agrees with the articles linked by Tony above. I was incorrect about the 2-capacitor-stack topology. Those articles tell how to reduce the flux walking problem.