fingering + vlsi
1) How transition time is going to effect your delay?
delay increases with transistion time.
2) If load is more, would delay increase or decrease?
why?
Delay increases with load. It requires more time to cahrge high loads.
3) How skew is goint to effect your setup and hold?
Will it help the setup?
setup time increases with skew.
4) If skew is more, how it is going to effect your
design?
The speed goes down with skew.
5) If phase delay is more, how it is going to effect
your design?
phase delay effects the frequency of operation due to phase distortion.
6) Why we need to fix the max transition before setup
and hold?
this effects delay.
7) What is meant by false path? When can we call
selection line of multiplexer as a false path? and
when not?
......
8) How we will decide the path as a false path? Can
you tell by taking mux as an example?
....
9) Why we need to fix hold after CTS only?
1.Explain multi cycle path with example and waveform
2.How is power consumption effected with shrinking technology?
3.What are the different types of placements?
4.How will u know whether to do a Timing Driven placement or Congestion Driven placement?
5.What does timing library consist of?
6.Look up tables?
7.how to calculate die size?
8.how to calculate the no of VDD and VSS pads?
9.Convert 2 i/p mux to inverter?
10.what is "set input delay" in sdc file?
11.During IPO upsizing and downsizing,what are upsized or downsized,FF's or Combi logic? Why?
12.Explain setup and hold with example and waveforms
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ST micro electronic question paper ST MICROELECTRONICS
ROUND 1
Que: CMOS working, Operation.
Que: Latch- Up
Que: Timing Slack, Setup, Hold, How to calculate the slack.
Que: Hot carrier effect?
Que: Pass transistor concept?
Que: How buffer minimizes skew as gate delays is more than propagation or transition
Delays?
ROUND2
Que: Difference between FF & Latch
Que: Racing Problem, what is it and where it occurs in FF or in latch?
Que: Block diag. Of latch.
Que: Slack
Que: Setup & Hold time? How is it effected?
Que: How to form cap in MOS? If Drain and source is shorted how will it behave
Like a capacitor? Which type of cap is it?
Que: Equation of VT ? where P.D. is more , where the gain is high?
ROUND – 3 (N Aggarwal)
Que: How will be Charging occur for the following Curve.
Que: How Mos device works?
Que: How CMOS Inverter works. How the N MOS/PMOS works in different region ie. Cut-off, saturation, linear.
Que: Equation of IDS in different region.
Que: Electro migration Calculation
Que: Antenna effect, from where the charge comes?
Que: where will we put the diode, nearer to gate or far from gate, & why?
Que: How layer hopping reduces the process Antenna effect?
Que: why distance between diffusion contacts?
ROUND 4
Que: cross section of MOS?
Que: cut it in half; how the view looks like?
Que: Guard Ring, secondary guard ring? Why is it always as ring?
Que: If u cut guard ring how will it look like?
Que: Latch Up?
Que: Antenna Effect?
Que: In the following figure what will happen if u run the metal1 Power supply 20v over
the poly.
Que: What were the problems u faced while doing layout?
Que: Tell about following fig. What actually it is?
Que: Is it possible to get +40 v if its supply is 515 in the following diagram?
Que: In diffusion region why multiple contact, what will happen if we put a big contact?
MEMORY GROUP
ROUND1
Que: Electro migration, & How will u overcome this & at what level u see it (In
Processing or after a chip is manufactured?)
Que: How will u calculate Electro migration & what r the data u need to calculate
E.M.? How fingering effects the E.M.?
Que: What is Antenna effect & How metal hopping improves antenna effects? (Positive
Charge gets collected on the metal, from where this charge comes?)
Que: Explain Latch up? How the Vdd value will come down to 0.9 if it is 5V earlier?
Que: How more substrate contact reduces +ve resistance and also well contact?
Que: How P tap / Ntap improves latch up?
Que: When does the ESD occurs? In processing or in operation?
Que: when does the Electro migration occurs? In processing or in Operation?
ROUND2
Que: How will u calculate the power stripe width?
Que: How will u improve IR drop effect?
Que: RC ckt. (Low pass Filter), o/p curve
Que: If u increase Vdd, what will be the effect on the sub threshold current?
Que: What kind of Capacitor is there in MOS? MOS device cap curve? Value of C
Substrate?
Que: DFM rule?
Que: How even no. of fingering is better than odd no. of fingering? How does it effect the
quality of layout?