# VLSI Interview QUESTIONS needed !!!!!!!!

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#### kinjalp

##### Newbie level 5 vlsi interview questions

hi
i am fresher in VLSI technology. I need to prepare for interview.
what are the best sites to prepare for interviews.
or which are the site where i can get some standard questions for interview along with answers ????

#### carrot

##### Full Member level 3 #### Guru59

##### Full Member level 4 antenna diode vlsi operation positive charge

Here are some Questions.........

Explain why & how a MOSFET works

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation

Explain the various MOSFET Capacitances & their significance

Draw a CMOS Inverter. Explain its transfer characteristics

Explain sizing of the inverter

How do you size NMOS and PMOS transistors to increase the threshold voltage?

What is Noise Margin? Explain the procedure to determine Noise Margin

Give the expression for CMOS switching power dissipation

What is Body Effect?

Describe the various effects of scaling

Give the expression for calculating Delay in CMOS circuit

What happens to delay if you increase load capacitance?

What happens to delay if we include a resistance at the output of a CMOS circuit?

What are the limitations in increasing the power supply to reduce delay?

How does Resistance of the metal lines vary with increasing thickness and increasing length?

You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

What happens if we increase the number of contacts or via from one metal layer to the next?

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Draw the stick diagram of a NOR gate. Optimize it

For CMOS logic, give the various techniques you know to minimize power consumption

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

Why don’t we use just one NMOS or PMOS transistor as a transmission gate?

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

Draw a 6-T SRAM Cell and explain the Read and Write operations

Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

What happens if we use an Inverter instead of the Differential Sense Amplifier?
Draw the SRAM Write Circuitry

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance?

What’s the critical path in a SRAM?

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

How can you model a SRAM at RTL Level?

What’s the difference between Testing & Verification?

For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

all the best....................

#### roy_ece

##### Member level 3 fingering + vlsi

1) How transition time is going to effect your delay?
delay increases with transistion time.
2) If load is more, would delay increase or decrease?
why?
Delay increases with load. It requires more time to cahrge high loads.
3) How skew is goint to effect your setup and hold?
Will it help the setup?
setup time increases with skew.
4) If skew is more, how it is going to effect your
design?
The speed goes down with skew.
5) If phase delay is more, how it is going to effect
phase delay effects the frequency of operation due to phase distortion.
6) Why we need to fix the max transition before setup
and hold?
this effects delay.
7) What is meant by false path? When can we call
selection line of multiplexer as a false path? and
when not?
......
8) How we will decide the path as a false path? Can
you tell by taking mux as an example?
....
9) Why we need to fix hold after CTS only?
1.Explain multi cycle path with example and waveform
2.How is power consumption effected with shrinking technology?
3.What are the different types of placements?
4.How will u know whether to do a Timing Driven placement or Congestion Driven placement?
5.What does timing library consist of?
6.Look up tables?
7.how to calculate die size?
8.how to calculate the no of VDD and VSS pads?
9.Convert 2 i/p mux to inverter?
10.what is "set input delay" in sdc file?
11.During IPO upsizing and downsizing,what are upsized or downsized,FF's or Combi logic? Why?
12.Explain setup and hold with example and waveforms

visit the site:
https://www.geocities.com/ramanjaneyuluv/vlsi_interview_questions.html

ST micro electronic question paper ST MICROELECTRONICS

ROUND 1

Que: CMOS working, Operation.
Que: Latch- Up
Que: Timing Slack, Setup, Hold, How to calculate the slack.
Que: Hot carrier effect?
Que: Pass transistor concept?
Que: How buffer minimizes skew as gate delays is more than propagation or transition
Delays?

ROUND2

Que: Difference between FF & Latch
Que: Racing Problem, what is it and where it occurs in FF or in latch?
Que: Block diag. Of latch.
Que: Slack
Que: Setup & Hold time? How is it effected?
Que: How to form cap in MOS? If Drain and source is shorted how will it behave
Like a capacitor? Which type of cap is it?
Que: Equation of VT ? where P.D. is more , where the gain is high?

ROUND – 3 (N Aggarwal)

Que: How will be Charging occur for the following Curve.

Que: How Mos device works?
Que: How CMOS Inverter works. How the N MOS/PMOS works in different region ie. Cut-off, saturation, linear.
Que: Equation of IDS in different region.
Que: Electro migration Calculation
Que: Antenna effect, from where the charge comes?
Que: where will we put the diode, nearer to gate or far from gate, & why?
Que: How layer hopping reduces the process Antenna effect?
Que: why distance between diffusion contacts?

ROUND 4

Que: cross section of MOS?
Que: cut it in half; how the view looks like?
Que: Guard Ring, secondary guard ring? Why is it always as ring?
Que: If u cut guard ring how will it look like?
Que: Latch Up?
Que: Antenna Effect?
Que: In the following figure what will happen if u run the metal1 Power supply 20v over
the poly.

Que: What were the problems u faced while doing layout?
Que: Tell about following fig. What actually it is?

Que: Is it possible to get +40 v if its supply is 515 in the following diagram?

Que: In diffusion region why multiple contact, what will happen if we put a big contact?

MEMORY GROUP

ROUND1
Que: Electro migration, & How will u overcome this & at what level u see it (In
Processing or after a chip is manufactured?)
Que: How will u calculate Electro migration & what r the data u need to calculate
E.M.? How fingering effects the E.M.?
Que: What is Antenna effect & How metal hopping improves antenna effects? (Positive
Charge gets collected on the metal, from where this charge comes?)
Que: Explain Latch up? How the Vdd value will come down to 0.9 if it is 5V earlier?
Que: How more substrate contact reduces +ve resistance and also well contact?
Que: How P tap / Ntap improves latch up?
Que: When does the ESD occurs? In processing or in operation?
Que: when does the Electro migration occurs? In processing or in Operation?

ROUND2

Que: How will u calculate the power stripe width?
Que: How will u improve IR drop effect?
Que: RC ckt. (Low pass Filter), o/p curve
Que: If u increase Vdd, what will be the effect on the sub threshold current?
Que: What kind of Capacitor is there in MOS? MOS device cap curve? Value of C
Substrate?
Que: DFM rule?
Que: How even no. of fingering is better than odd no. of fingering? How does it effect the
quality of layout?

#### avimit

##### Banned #### meetspraveen

##### Member level 2 effects of electromigration on vlsi layouts

hi
asic.co.in is very useful

##### Full Member level 5 various mosfet capacitances & their significance

#### shavakmm

##### Member level 4 #### vlsi_freak

##### Full Member level 2 mos questions vlsi

Hi.

Lots of questions and issues discussed in this board. Make your digital basics strong.
If you know any of the HDL will be plus point; concentrate on that also.

Thanks

V
Points: 2