vreg
Member level 4

Hi,
Can someone suggest any open design problems in vlsi architectures that can lead to publishable results - for example any optimizations that can be done in existing implementation of a specific protocol, open issues to solve, etc...
I want to code in verilog and synthesize the complete circuit.
(must be completable in 3-4 months span)
Thanks...
Can someone suggest any open design problems in vlsi architectures that can lead to publishable results - for example any optimizations that can be done in existing implementation of a specific protocol, open issues to solve, etc...
I want to code in verilog and synthesize the complete circuit.
(must be completable in 3-4 months span)
Thanks...