(parameterinteger INPUT_QUEUE_DEPTH =4,parameterinteger N =5,parameterinteger M =5)genvar i;generatefor(i=0; i<N; i++)begin: GENERATE_VOQ
LIB_VOQ #(.M(M), .DEPTH(INPUT_QUEUE_DEPTH))
gen_LIB_VOQ (.clk,
.ce,
.reset_n,
.i_data(l_i_data[i]),// Single input data from upstream router
.i_data_val(l_vc_req[i]),// Valid from routecalc corresponds to required VC
.o_en(l_o_en[i]),
.o_data(l_data[i]),// Single output data to switch
.o_data_val(l_output_req[i]),// Packed request word to SwitchControl
.i_en(l_en[i]));// Packed grant word from SwitchControlendendgenerate
gives the error
[Synth 8-196] conditional expression could not be resolved to a constant ["filename":158]
where line 158 is the line
Code Verilog - [expand]
1
for(i=0; i<N; i++)begin: GENERATE_VOQ
- - - Updated - - -
I just added a space after for and it started to synthesize.
//synthesizes
count_reg <= count_reg +1;// ads-ee: This is legal Verilog syntax//fails
count_reg <= count_reg++;// ads-ee: This isn't leagal Verilog or System Verilog syntax, so why are you giving a "C" sytnax example?//for loop syntaxfor(i=0; i<N; i=i+1)begin: GENERATE_VOQ // ads-ee: this is leagal Verilog syntax//for loop syntaxfor(i=0; i<N; i++)begin: GENERATE_VOQ // ads-ee: this is leagal System Verilog syntax, which Vivado does support for synthesis,// but according to the OP the parser has a problem with "for(" (no space) and doesn't with "for (" (with space).