BartlebyScrivener
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When I try to synthesize with Vivado It seems to not like the way I do my generate loops ... I get the following error
But the code works in simulation, and synthesis with quartus. Googling the error doesn't bring up anything really.
What could this be? This is my first attempt with Vivado so it may be silly, but the way I write my generate loops is as follows.
Thanks/
Code:
[Synth 8-196] conditional expression could not be resolved to a constant [filename]
But the code works in simulation, and synthesis with quartus. Googling the error doesn't bring up anything really.
What could this be? This is my first attempt with Vivado so it may be silly, but the way I write my generate loops is as follows.
Code Verilog - [expand] 1 2 3 4 5 6 genvar i; generate for (i=0; i<M; i++) begin : VIRTUAL_CHANNELS // code here end endgenerate
Thanks/