Viterbi Decoding Error

[Abhijith Yadav]

Hey people,
I am working on viterbi decoding in vhdl. I am using altera quartusII 6.0. I am posting the code and the problem, please help me rectifyy ut

library ieee;
library work;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.data_packages.all;

entity viterbi_decode is
	port (path_calc: buffer statehist_data;
		  enc_data : in std_logic_vector(1 downto 0);
		  clock    : in std_logic;
		  xor_out  : buffer output_data;
		  pm       : buffer pmetric;
		  path	   : buffer statehist_data;
		  pathfinal: out std_logic_vector(14 downto 0));
end viterbi_decode;

architecture func of viterbi_decode is

component A is
port (xor_out               : buffer output_data;
	  path                  : buffer statehist_data;
	  bm                    : in  bmetric;
	  pathmetricA           : buffer integer range 0 to 1023;
      pm                    : out pmetric);
end component;

component B is
port (xor_out               : buffer output_data;
	  path                  : buffer statehist_data;
	  bm                    : in  bmetric;
	  pathmetricB           : buffer integer range 0 to 1023;
      pm                    : out pmetric);
end component;

component C is
port (xor_out               : buffer output_data;
	  path                  : buffer statehist_data;
	  bm                    : in  bmetric;
	  pathmetricC           : buffer integer range 0 to 1023;
      pm                    : out pmetric);
end component;

component D is
port (xor_out               : buffer output_data;
	  path                  : buffer statehist_data;
	  bm                    : in  bmetric;
	  pathmetricD           : buffer integer range 0 to 1023;
      pm                    : out pmetric);
end component;

component viterbi_table is
 port(bm                :buffer bmetric;
	  enc_data          :in     std_logic_vector(1 downto 0);
      xor_out           :buffer output_data);
end component;

signal ct: integer range 0 to 20:=0;

begin
--path_calc<=path;
process(xor_out,ct,clock,path,enc_data)
begin
	if(rising_edge(clock)) then
	path_calc<=path;
		ct<=ct+1;
		if(ct=1) then
		xor_out(0)<=enc_data xor "00";
		xor_out(1)<=enc_data xor "11";
		path(2)(14 downto 0)<=path(0)(13 downto 0);
		path(2)(0)<='1';
		for i in 0 to 1 loop
			if (xor_out(0)(i)=1) then
			pm(0)<=pm(0)+1;
			end if;
			if (xor_out(1)(i)=1) then 
			pm(2)<=pm(2)+1;
			end if;
		end loop;
		elsif(ct+2) then
		xor_out(0)<=enc_data xor "00";
		xor_out(1)<=enc_data xor "11";
		xor_out(4)<=enc_data xor "10";
		xor_out(5)<=enc_data xor "01";
		path(1)(14 downto 1)<=path(2)(13 downto 0);
		path(1)(0)<='0';
		path(3)(14 downto 1)<=path(2)(13 downto 0);
		path(3)(0)<='1';
		path(2)(14 downto 1)<=path(0)(13 downto 0);
		path(2)(0)<='1';
		for i in 0 to 1 loop
		if ( xor_out(0)(i)='1') then
		pm(0)<=pm(0)+1;
		end if;
		if ( xor_out(1)(i)='1') then
		pm(1)<=pm(1)+1;
		end if;
		if ( xor_out(4)(i)='1') then
		pm(1)<=pm(4)+1;
		end if;
		if ( xor_out(5)(i)='1') then
		pm(5)<=pm(5)+1;
		end if;
		end loop;
		end if;
		viterbi: for ct in 2 to 15 generate
			bm(0)<=pm(0);
			bm(1)<=pm(0);
			bm(2)<=pm(1);
			bm(3)<=pm(1);
			bm(4)<=pm(2);
			bm(5)<=pm(2);
			bm(6)<=pm(3);
			bm(7)<=pm(3);
			Table: Viterbi_table port map(bm,enc_data,xor_out);
			atA: A port map(xor_out,path,bm,pm(0),pm);
			atB: B port map(xor_out,path,bm,pm(1),pm);
			atC: C port map(xor_out,path,bm,pm(2),pm);
			atD: D port map(xor_out,path,bm,pm(3),pm); 
		end generate;
		ct<=0;
		end if;
		end if;
end process;
end func;

the code for viterbi_table

library ieee;
library work;
use work.data_packages.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity viterbi_table is
 port(bm                :buffer bmetric;
	  enc_data          :in     std_logic_vector(1 downto 0);
      xor_out           :buffer output_data);
end viterbi_table;

architecture func of viterbi_table is 
signal output:output_data;
begin
output(0)<="00";
output(1)<="11";
output(2)<="11";
output(3)<="00";
output(4)<="10";
output(5)<="01";
output(6)<="01";
output(7)<="10";
process(enc_data,output,xor_out,bm)
begin
for i in 0 to 7 loop
xor_out(i)<=enc_data xor output(i);
	for j in 0 to 1 loop
		if ( xor_out(i)(j)='1') then
   			bm(i)<=bm(i)+1;
		end if;
	end loop;
end loop ;
end process;
end func;

code for A,B,C,D:

library ieee;
library work;
use work.data_packages.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

entity A is
port (xor_out               : buffer output_data;
	  path                  : buffer statehist_data;
	  bm                    : in  bmetric;
	  pathmetricA           : buffer integer range 0 to 1023;
      pm                    : out pmetric);
 end A;

architecture func of A is
signal pmetric_calc: metric_calc;
signal path_calc   : statehist_data;
begin
path_calc(0)<=path(0);
path_calc(1)<=path(1);
path_calc(2)<=path(2);
path_calc(3)<=path(3);
process(pmetric_calc,bm,path_calc,pathmetricA)
begin
pmetric_calc(0)<=pathmetricA+bm(0);
pmetric_calc(1)<=pathmetricA+bm(2);
	if (pmetric_calc(0)<pmetric_calc(1)) then 
		pathmetricA<=pmetric_calc(0);
		path(0)(14 downto 1)<=path_calc(0)(13 downto 0);
		path(0)(0)<='0';
	elsif(pmetric_calc(0)>pmetric_calc(1)) then
		pathmetricA<=pmetric_calc(1);
		path(0)(14 downto 1)<=path_calc(1)(13 downto 0);
		path(0)(0)<='0';
	end if;
end process;
end func;

library ieee;
library work;
use work.data_packages.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

entity B is
port (xor_out               : buffer output_data;
	  path                  : buffer statehist_data;
	  bm                    : in  bmetric;
	  pathmetricB           : buffer integer range 0 to 1023;
      pm                    : out pmetric);
 end B;

architecture func of B is
signal pmetric_calc: metric_calc;
signal path_calc   : statehist_data;
begin
path_calc(0)<=path(0);
path_calc(1)<=path(1);
path_calc(2)<=path(2);
path_calc(3)<=path(3);
process(pmetric_calc,bm,path_calc,pathmetricB)
begin
pmetric_calc(0)<=pathmetricB+bm(4);
pmetric_calc(1)<=pathmetricB+bm(6);
	if (pmetric_calc(0)<pmetric_calc(1)) then 
		pathmetricB<=pmetric_calc(0);
		path(1)(14 downto 1)<=path_calc(1)(13 downto 0);
		path(1)(0)<='0';
	elsif(pmetric_calc(0)>pmetric_calc(1)) then
		pathmetricB<=pmetric_calc(1);
		path(1)(14 downto 1)<=path_calc(1)(13 downto 0);
		path(1)(0)<='0';
	end if;
end process;
end func;

library ieee;
library work;
use work.data_packages.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

entity C is
port (xor_out               : buffer output_data;
	  path                  : buffer statehist_data;
	  bm                    : in  bmetric;
	  pathmetricC           : buffer integer range 0 to 1023;
      pm                    : out pmetric);
 end C;

architecture func of C is
signal pmetric_calc: metric_calc;
signal path_calc   : statehist_data;
begin
path_calc(0)<=path(0);
path_calc(1)<=path(1);
path_calc(2)<=path(2);
path_calc(3)<=path(3);
process(pmetric_calc,bm,path_calc,pathmetricC)
begin
pmetric_calc(0)<=pathmetricC+bm(1);
pmetric_calc(1)<=pathmetricC+bm(3);
	if (pmetric_calc(0)<pmetric_calc(1)) then 
		pathmetricC<=pmetric_calc(0);
		path(2)(14 downto 1)<=path_calc(2)(13 downto 0);
		path(2)(0)<='1';
	elsif(pmetric_calc(0)>pmetric_calc(1)) then
		pathmetricC<=pmetric_calc(1);
		path(2)(14 downto 1)<=path_calc(2)(13 downto 0);
		path(2)(0)<='1';
	end if;
end process;
end func;

library ieee;
library work;
use work.data_packages.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

entity D is
port (xor_out               : buffer output_data;
	  path                  : buffer statehist_data;
	  bm                    : in  bmetric;
	  pathmetricD           : buffer integer range 0 to 1023;
      pm                    : out pmetric);
 end D;

architecture func of D is
signal pmetric_calc: metric_calc;
signal path_calc   : statehist_data;
begin
path_calc(0)<=path(0);
path_calc(1)<=path(1);
path_calc(2)<=path(2);
path_calc(3)<=path(3);
process(pmetric_calc,bm,path_calc,pathmetricD)
begin
pmetric_calc(0)<=pathmetricD+bm(5);
pmetric_calc(1)<=pathmetricD+bm(7);
	if (pmetric_calc(0)<pmetric_calc(1)) then 
		pathmetricD<=pmetric_calc(0);
		path(3)(14 downto 1)<=path_calc(3)(13 downto 0);
		path(3)(0)<='1';
	elsif(pmetric_calc(0)>pmetric_calc(1)) then
		pathmetricD<=pmetric_calc(1);
		path(3)(14 downto 1)<=path_calc(3)(13 downto 0);
		path(3)(0)<='1';
	end if;
end process;
end func;

data package :

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

package data_packages is
 type statenew_data  is array(7 downto 0) of std_logic_vector(1 downto 0);
 type statehist_data is array(3 downto 0) of std_logic_vector(14 downto 0);
 type state_data     is array(7 downto 0) of std_logic_vector(1 downto 0);
 type output_data    is array(7 downto 0) of std_logic_vector(1 downto 0);
 type bmetric        is array(7 downto 0) of integer range 0 to 2;
 type pmetric        is array(3 downto 0) of integer range 0 to 1023;
 type metric_calc    is array(1 downto 0) of integer range 0 to 1023;
end;

- - - Updated - - -

The errors are as follows

Error (10500): VHDL syntax error at Viterbi_decode.vhd(105) near text "generate"; expecting "loop"
Error (10500): VHDL syntax error at Viterbi_decode.vhd(114) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at Viterbi_decode.vhd(114) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at Viterbi_decode.vhd(115) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at Viterbi_decode.vhd(115) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at Viterbi_decode.vhd(116) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at Viterbi_decode.vhd(116) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at Viterbi_decode.vhd(117) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at Viterbi_decode.vhd(117) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at Viterbi_decode.vhd(118) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at Viterbi_decode.vhd(118) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at Viterbi_decode.vhd(122) near text "if"; expecting "process"

- - - Updated - - -

In addition to that, I have a query.. is it wrong to use component instantiation inside a process or a conditional loop

 

[axcdd]

Im sorry but its forbidden to use component declarations in processes.
Your blocks A B C D are simple combination logic so i suggest write them as a functions and add them to data_package and then change generic in viterbi_decode to simple loop with function declarations within

There is possibility to use components initiation in conditional loop such as: (exp without a loop)
condition1: if sth = true generate
--possible loop here
component(i): mycomponent port map .....
-- end possible loop here
end generate;

 

[Abhijith Yadav]

how do i use packages for the task... can i include all the functions i need in the same package? Also, if i write different components one after the other in the viterbi_decode WITHOUT a loop or process, will they execute iteratively (or simply,loop after completing the last component in order) if the component called for has a process satetement checking for rising edge of clock



like for ex:

A:A port map....
B:B port map....
.
.
.
.
.
.
L:L port map....


if the component A has a loop based on rising edge of a clock will it be executed again after the completion of L?

 

[Abhijith Yadav]

the following is the code i wrote afresh for the same decoding scheme.....

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.data_packages.all;

entity Viterbi_new is 
port (clock: in std_logic;
	  --ct: buffer integer range 0 to 16;
	  enc_data: in std_logic_vector(1 downto 0);
	  dec_data: out std_logic_vector(14 downto 0));
end Viterbi_new;

architecture decode of Viterbi_new is
signal metricfinalA: integer range 0 to 30:=1;
signal metricfinalB: integer range 0 to 30:=1;
signal metricfinalC: integer range 0 to 30:=1;
signal metricfinalD: integer range 0 to 30:=1;
signal pathfinalA: std_logic_vector(14 downto 0);
signal pathfinalB: std_logic_vector(14 downto 0);
signal pathfinalC: std_logic_vector(14 downto 0);
signal pathfinalD: std_logic_vector(14 downto 0);
--signal ct:integer range 0 to 16;
signal metricind_A: metricind_data;
signal metricind_B: metricind_data;
signal metricind_C: metricind_data;
signal metricind_D: metricind_data;
signal pathind_A: pathind_data;
signal pathind_B: pathind_data;
signal pathind_C: pathind_data;
signal pathind_D: pathind_data;
signal xorA : xor_data;
signal xorB : xor_data;
signal xorC : xor_data;
signal xorD : xor_data;
signal outA:xor_data;
signal outB:xor_data;
signal outC:xor_data;
signal outD:xor_data;
signal zero:std_logic;
signal pathfinal: std_logic_vector(14 downto 0);
signal metric_decide: integer range 0 to 30;
signal path_finals: pathfinal_data;
signal metricfinals:metricfinal_data;
begin
process(pathfinal,clock,enc_data,xorA,xorB,xorC,xorD,pathind_A,pathind_B,pathind_C,pathind_D,metricind_A,metricind_B,metricind_C,metricind_D,outA,outB,outC,outD)
begin
outA(0)<="00";
outA(1)<="11";
outB(0)<="11";
outB(1)<="00";
outC(0)<="10";
outC(1)<="01";
outD(0)<="01";
outD(1)<="10";
if (rising_edge(clock)) then
	--ct<=ct+1;
for j in 0 to 15 loop
	--ct<=ct+1;
	pathind_A(0)(14 downto 1)<=pathfinalA(13 downto 0);
	pathind_A(1)(14 downto 1)<=pathfinalB(13 downto 0);
	pathind_B(0)(14 downto 1)<=pathfinalC(13 downto 0);
	pathind_B(1)(14 downto 1)<=pathfinalD(13 downto 0);
	pathind_C(0)(14 downto 1)<=pathfinalA(13 downto 0);
	pathind_C(1)(14 downto 1)<=pathfinalB(13 downto 0);
	pathind_D(0)(14 downto 1)<=pathfinalC(13 downto 0);
	pathind_D(1)(14 downto 1)<=pathfinalD(13 downto 0);
	pathind_A(0)(0)<='0';
	pathind_A(1)(0)<='0';
	pathind_B(0)(0)<='0';
	pathind_B(1)(0)<='0';
	pathind_C(0)(0)<='1';
	pathind_C(1)(0)<='1';
	pathind_D(0)(0)<='1';
	pathind_D(1)(0)<='1';
		for i in 0 to 1 loop
			xorA(i)<=outA(i) xor enc_data;
			xorB(i)<=outB(i) xor enc_data;
			xorC(i)<=outC(i) xor enc_data;
			xorD(i)<=outD(i) xor enc_data;
		end loop;
		for i in 0 to 1 loop
 			if(xorA(0)(i)<='1') then
			metricind_A(0)<=metricfinalA+1;
			end if;
			if(xorA(1)(i)<='1') then
			metricind_A(1)<=metricfinalB+1;
			end if;
			if(xorB(0)(i)<='1') then
			metricind_B(0)<=metricfinalC+1;
			end if;
			if(xorB(1)(i)<='1') then
			metricind_B(1)<=metricfinalD+1;
			end if;
			if(xorC(0)(i)<='1') then
			metricind_C(0)<=metricfinalA+1;
			end if;
			if(xorC(1)(i)<='1') then
			metricind_C(1)<=metricfinalB+1;
			end if;
			if(xorD(0)(i)<='1') then
			metricind_D(0)<=metricfinalC+1;
			end if;
			if(xorD(1)(i)<='1') then
			metricind_D(1)<=metricfinalD+1;
			end if;
		end loop;
		if(metricind_A(0)<metricind_A(1)) then
		pathfinalA<=pathind_A(0);
		metricfinalA<=metricind_A(0);
		elsif(metricind_A(0)>metricind_A(1)) then
		pathfinalA<=pathind_A(1);
		metricfinalA<=metricind_A(1);
		end if;
		if(metricind_B(0)<metricind_B(1)) then
		pathfinalB<=pathind_B(0);
		metricfinalB<=metricind_B(0);
		elsif(metricind_B(0)>metricind_B(1)) then
		pathfinalB<=pathind_B(1);
		metricfinalB<=metricind_B(1);
		end if;
		if(metricind_C(0)<metricind_C(1)) then
		pathfinalC<=pathind_C(0);
		metricfinalC<=metricind_C(0);
		elsif(metricind_C(0)>metricind_C(1)) then
		pathfinalC<=pathind_C(1);
		metricfinalC<=metricind_C(1);
		end if;
		if(metricind_D(0)<metricind_D(1)) then
		pathfinalD<=pathind_D(0);
		metricfinalD<=metricind_D(0);
		elsif(metricind_D(0)>metricind_D(1)) then
		pathfinalD<=pathind_D(1);
		metricfinalD<=metricind_D(1);
		end if;
		metricfinals(0)<=metricfinalA;
		metricfinals(1)<=metricfinalB;
		metricfinals(2)<=metricfinalC;
		metricfinals(3)<=metricfinalD;
		path_finals(0)<=pathfinalA;
		path_finals(1)<=pathfinalB;
		path_finals(2)<=pathfinalC;
		path_finals(3)<=pathfinalD;
end loop;
--if (ct>15) then
	pathfinal<=path_finals(0);
	metric_decide<=metricfinals(0);
	for i in 1 to 3 loop
	if(metricfinals(i)>metric_decide) then
	metricfinals(i)<=metric_decide;
	pathfinal<=path_finals(i);
	end if;
	end loop;
--end if; 
end if;
dec_data<=pathfinal;
end process;
--dec_data<=pathfinal;
end decode;

data_packages_2:

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

package data_packages is 
type pathfinal_data   is array (3 downto 0) of std_logic_vector(14 downto 0);
type xor_data         is array (1 downto 0) of std_logic_vector(1 downto 0);
type metricind_data   is array (1 downto 0) of integer range 0 to 30;
type metricfinal_data is array (3 downto 0) of integer range 0 to 30;
type pathind_data     is array (1 downto 0) of std_logic_vector(14 downto 0);
end;

the following are the warnings im receiving after compilation

Warning: Reduced register "pathind_D[0][0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_D[1][0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_C[0][0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_C[1][0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_B[0][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathind_B[1][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathind_A[0][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathind_A[1][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalA[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalB[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalC[0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathfinalD[0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_A[1][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathind_A[0][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathind_B[1][1]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_B[0][1]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_C[1][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathind_C[0][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathind_D[1][1]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_D[0][1]" with stuck data_in port to stuck value VCC
Warning: Reduced register "path_finals[0][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[1][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[2][0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "path_finals[3][0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathfinalA[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalB[1]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathfinalC[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[1]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_A[1][2]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_A[0][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathind_B[1][2]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_B[0][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathind_C[1][2]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_C[0][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathind_D[1][2]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathind_D[0][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[0][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[1][1]" with stuck data_in port to stuck value VCC
Warning: Reduced register "path_finals[2][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][1]" with stuck data_in port to stuck value VCC
Warning: Reduced register "metricfinalD[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinalD[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinalD[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinalD[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinalD[0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "pathfinalD[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinalD[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][3]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][4]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][5]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][6]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][7]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][8]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][9]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][10]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][11]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][12]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][13]" with stuck data_in port to stuck value GND
Warning: Reduced register "path_finals[3][14]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[0][4]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[0][3]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[0][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[0][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "pathfinal[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "metric_decide[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "metric_decide[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "metric_decide[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "metric_decide[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[3][4]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[3][3]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[3][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[3][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[2][4]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[2][3]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[2][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[2][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[1][4]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[1][3]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[1][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "metricfinals[1][1]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
Warning: Pin "dec_data[2]" stuck at GND
Warning: Pin "dec_data[3]" stuck at GND
Warning: Pin "dec_data[4]" stuck at GND
Warning: Pin "dec_data[5]" stuck at GND
Warning: Pin "dec_data[6]" stuck at GND
Warning: Pin "dec_data[7]" stuck at GND
Warning: Pin "dec_data[8]" stuck at GND
Warning: Pin "dec_data[9]" stuck at GND
Warning: Pin "dec_data[10]" stuck at GND
Warning: Pin "dec_data[11]" stuck at GND
Warning: Pin "dec_data[12]" stuck at GND
Warning: Pin "dec_data[13]" stuck at GND
Warning: Pin "dec_data[14]" stuck at GND
Warning: Design contains 2 input pin(s) that do not drive logic
Warning: No output dependent on input pin "enc_data[0]"
Warning: No output dependent on input pin "enc_data[1]"


please help me solve the issue

 

[TrickyDicky]

It has determined that those registers are stuck at 0 or 1, hence the warning about removal. Its probably because is clock, clock enable or reset is stuck at '1' or '0'. Have you testbenched this code?

 

[Abhijith Yadav]

i dont know how to test bench.. can u please tell me how to do tht

 

[lucbra]

A little weird that you perfectly know how to write good (sort of) VHDL, and don't know how to build a test bench.

Take a book about VHDL, open it up at chapter 9 or 10 - test benches, define your stimuli, that's it.

 

[TrickyDicky]

I would also suggest a newer version of quartus - V6 is about 7 years old!

 

[Abhijith Yadav]

Are u talking about the simulator, i mean vector waveform file? In that case, I dop know what tht is and have tried it for the program... But to no avail

- - - Updated - - -

Also, is it possible to get a newer version of quartus. I mean for free..... And if i do, will I get to configure a FPGA with tht version itself?

 

[TrickyDicky]

It depends what your chip is. If its a cyclone 1, you'll probably have to stick with the version you got.

 

[Abhijith Yadav]

mine is altera 7160slc.... should i stick to my version or is better one preferred... please post link for the download page, and please answer my other question , "Are u talking about the simulator, i mean vector waveform file? In that case, I dop know what tht is and have tried it for the program... But to no avail". thanks in advance

 

[TrickyDicky]

The downloads are on the altera website. Ill let you go look yourself. THe 7160slc is a very old Max7000 device. Support for it was probably dropped in quartus 9.1.

When we talk about simulation, usually that is performed in a 3rd party RTL simulator (like modelsim) using a testbench you created yourself. waveform files are not a very powerful tool.

 

[Abhijith Yadav]

so can i configure my fpga with the downloadable version of altera.... or do i need to buy it to be able to do tht?

 

[TrickyDicky]

You might be able to use an old version of the web edition, but I dont know. It would be best to stick with the version you have if it works.

 

[Abhijith Yadav]

thanks for the help.... I will get back to you if any prblems occur