neethusebastian
Newbie level 2
- Joined
- Oct 8, 2013
- Messages
- 2
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1
- Activity points
- 8
i am doing a project of convolutional encoder with viterbi decoder with K=7 AND r=1/2 ....am also using FPGA for implementing it...so i need VERILOG HDL code of it and i have more doubts about this project....please kindly help me to doing this