Virtuoso 6.1.4: Technology files

[TurnN]

Hi.

I study a non-semiconuctor computing device and use Virtuoso 6.1.4 as EDA tool.

I'm making a technology file for the device, and I'm having a problem.

I wrote below in the .tf file:

constraintGroups(

(foundry

interconnect(

(validLayers ("L1" "L2" "L3" "L4"))

(validVias ("V1"))

(validVias

(

(("width" nil nil "width" nil nil) (V1))

(

(15.0 15.0) (V1)

)

)

)

);interconnect
spacings(...)
);foundry
);constraintGroups


However, when I convert a schematic to layout, the following error appears:
*WARNING* (LX-2063): The technology library 'adp619Refine' contains no constraint groups that have
a 'validLayers' or 'validVias' constraint defined. Thus the XL connectivity extractor is disabled.
To enable it, add a 'validLayers' constraint to the appropriate constraint group, and ensure that
this constraint group is specified by the 'setupConstraintGroup' environment variable.


What is wrong? Please help me.

 

[ZeDingo]

Have you renamed an alias related to your technology files? https://groups.google.com/forum/#!topic/comp.cad.cadence/sQ6Gm2qmUhc

 

[TurnN]

> Have you renamed an alias related to your technology files? https://groups.google.com/forum/#!to...ce/sQ6Gm2qmUhc

maybe? What I've done is:
1. copy an existing old library "ORIGINAL" to "COPY"("I cannot modify the master data)
2. dump the .tf from "COPY"
3. modify .tf
4. replace the technology file of "COPY"
5. make a new library "NewLibTest" using "Attach to an existing technology library"(existing technology library="COPY")
6. make a new cellview in "NewLibTest"