In my layout I assign the port material to be "metal 6 pn", but the LVS reports me that the ports are missing. I am working on ST foundry and my verification tool is calibre.
I have tried Metal 6 PN for the port and tt for the Text, Metal 6 PN for port and Metal 6 PT for text, and several others combinations for 3 days now... ;(
What should be the problems? Is there a specific combination for ST, or something else is wrong?
Thank you!!!
--------------------------------
REPORT FROM LVS:
--------------------------------
LAYOUT NAME SOURCE NAME
Discrepancy #1 in LNA_1st_sing
** missing port ** VDD on net: VDD
Discrepancy #2 in LNA_1st_sing
** missing port ** gnd on net: gnd
Discrepancy #3 in LNA_1st_sing
** missing port ** RF on net: RF
Discrepancy #4 in LNA_1st_sing
** missing port ** OUT on net: OUT
Discrepancy #5 in LNA_1st_sing
** missing port ** _V1 on net: _V1
Discrepancy #6 in LNA_1st_sing
This might be an obvious question, but, is there a label or 'lbl' subtype on metal 6?
- - - Updated - - -
Oh, I just saw your attachment. The cross doesn't seem to be overlapping the metal. Try putting the label right on top of the metal, it might not be attached to any metal and Calibre LVS is just ditching it.
I tried that already, but I get a warning which stops the LVS.
WARNING: Open circuit - Same name on different nets:
Name: "OUT+"
(1) at location (1125.179,779.203) on layer 136 "METAL6_pintext" on net id 8
(2) at location (1125.179,779.203) on layer 3136 on net id 38
The name was assigned to net 8 .
This is the right thing to do, it should be on top. At least it detects the label now --- the only problem is that it sees it twice.
Attempt 1:
There is a darker brown square at the edge of the wire. What material is that? if you click on properties of that square can you
check the net name is set to OUT?
Attempt 2:
Try to put the label in 'Metal 6 drawing (dg)' or literally go through all the types to see if one of them works.
I am not familiar with STmicro GDS stack.