[SOLVED] Virtex 6 Embedded Tri-mode Ethernet MAC wrapper interface

[NIJIL N]

Hi,
I have tried to implement the example design which provided with "Virtex 6 Embedded Tri-mode Ethernet MAC wrapper v2.3" in Core generator,on virtex 6 development board(ML605)
When I program it on the board , the packets were successfully received by the FPGA,but the board is not transmitting back the packets.I am using "Wireshark" for analysing the packets and packETH for transmitting the packets.

Please Help,
I am confused...

 

[Port Map]

Plz bring some more information!

Which mode are you using, MII/GMII/RGMII/SGMII..?
If you directly connected PC to Board, are your cable crossed over?
How about link speed? did you tried to fix the network adapter speed on 100Mbps or 1Gbps?
Is UCF file correct?

I had problem like this, and my test was OK with 1Gbps link but was not OK with 100Mbps link!

 

[NIJIL N]

My setup:
I directly connected the board to PC via an Ethernet cable,regular one (cat 5 or 5e not sure).I set the jumpers ,programmed the board and tried to run it. Didn't use any switch in between .
I am using GMII mode.I did not change anything in the UCF file.I Don know about the link speed.
But when am transmitting the packets ,An Led near the Ethernet port in the board blinks.

Thanks in advance

 

[Port Map]

My setup:
But when am transmitting the packets ,An Led near the Ethernet port in the board blinks.

This Led says that packets are received to Phy not to FPGA.
I think you need some steps to complete the test.

1. check that PHY reset signal correctly applied. I think you will need a not on this signal before living FPGA.
2. about link speed: u can set it on network adapter advanced settings.
3. If u used the cable shipped with ML605 that's true because it's a crossover cable.

 

[NIJIL N]

Issue is solved,the problem was with the link speed. When i set it to 1Gbps in PC ,board is transmitting back the packets.

Thanku Port Map..Thanks a lot