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Virtex 5 Rocket IO design for reading in ADC data.

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Full Member level 5
Dec 1, 2009
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Hello all,

I am presently working with a virtix 5 FPGA and trying to get the rocket IOs to work with reading in the data generated from my ADC. The ADC is clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my data 4 bits transitioning at 250Mhz. I am then configuring the FPGA to store the data after it has been serial to parallel converted within the FPGA then I read it out later after it has taken the data so I can process my FFT in matlab. My problem is I know my ADC is working since I first took the data over a scope, but I want to speed up the measuring process by using a cool and fancy FPGA. My question is, can any help me in setting up the rocket IOs so ensure it does not miss any bits or transitions? If 1 in just 1000 samples it wrong my FFT is completely crap and I cant use it!

My present setup, which I have no clue if I am correct, is I use the rockets to sync to the incoming data (250MHz bits) only ( not the output clock). I then use the same clock recovered for the data to then clock the data into memory. My question is, is there a better way to do this? Cant i use my 500MHz clock to just clock the other data rocket IOs or since the rocket IOs work off of a PLL, I cant do that.....

Any help would be great.



I have done something similar on Spartan6. The point is don't use the GTPs for that, but use normal IO pins in differential mode, use the IDDR primitives, and local IO clock networks to clock the IDDRs. I think this is the usual way and it worked for me. Make sure that all inputs are on diff-inpput-capable pins and also that they are in the same IO-clock (BUFIO) region. Coregenerator can generate your IO logic for you, but you have to be careful with the pin assigment.


Thanks for the reply,

So isn't it a problem with my speed of 500MHz? also on my next chip I will be at 1GHz. So using the normal pins this is not possible I would think.... In using the rocket IOs , the IOs sample stuff in serial then convert it parallel as to keep up with the high data rate. What speed were you sampling at and what was your FPGA clocked at?


For the rocket IO transceivers you need a signal which has the clock embedded into it.
Most probably your ADC provides a separate IO clock signal to sample the data, this way the GTP is not suitable for it.
Check your FPGA electrical datasheet for max speed of: IO-buffer, IDDR, BUFIO (its an IO clock network actually), PLL.
I have used Spartan-6 which works up to 1GT/s on the IO circuits with the highest speed grade part. I have used at 400MT/s double data rate LVDS with 200MHz IO clock.

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