Virtex-5 IOBs swing capability

[msdarvishi]

Hello everybody,

I am working with Digilent Xilinx Gensys board including Virtex-5 (XC5VLX50T) FPGA. I used the internal 200MHz clock created by IDT...9885 module as the input frequency of DCM and I am trying to monitor the CLKIN (input) and CLK0 (output) of DCM simultaneously by changing the DSKEW_ADJUST parameter...

I used a Tektronix CSA7404B Signal Analyzer for measurement with 4GHz and 20GS/s. As you see in the attached figures, I supposed to see a 200MHz square wave as input while I see a 200MHz sine wave. I also measured the CLK/16 signal (which is 200MHz/16 = 12.5MHz) and as shown, it is a fine square wave.

Can anybogy tell me what is going wrong with the 200MHz signal? Why I cannot see the square wave? Are the PMOD connectors are capable to handle this frequency? Or are the IOBs swing in Virtex-5 is defined for this frequency?

I also added the picture of the probe that I used for my meausurements.



Thank you all,

 

[ads-ee]

You are looking at a differential LVDS clock with a single ended probe. That's why the signal has a DC offset from ground and a ~800mV swing.

 

[msdarvishi]

You are looking at a differential LVDS clock with a single ended probe. That's why the signal has a DC offset from ground and a ~800mV swing.

Hello @ads-ee,
If you look at the RTL schematic attached, you will see that I buffered the differential clock with IBUFGDS and it is single ended... If so, can you please guide me how to overcome this problem?

Thank you,

 

[ads-ee]

What problem? a differential input clock will never look like a square wave.

If you want a square wave input clock use a single ended clock source.

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If you look at the RTL schematic attached, you will see that I buffered the differential clock with IBUFGDS and it is single ended... If so, can you please guide me how to overcome this problem?

Oh, I'm sorry I misinterpreted what you were doing...

You pulled the top off the package and exposed the die and are probing the output of the IBUFGDS single ended output which is has something like a 32nm channel width with your >1um scope probe tip.

I suggest you use an electron microscope and a Tektronix probe with a 10nm tip to measure the clock on the IBUFGDS single ended otuput. :-D

 

[mrflibble]

If you look at the RTL schematic attached, you will see that I buffered the differential clock with IBUFGDS and it is single ended... If so, can you please guide me how to overcome this problem?

You can overcome this problem by licking an lsd laced sugar cube to rewire some neural paths. The paths related to your expectation value to be precise. In a pinch some pink elephant tea might also do the trick.

As ads-ee jokingly already hinted at, the IBUFGDS related signal that you can probe with a physical oscilloscope probe is a differential signal. And as such you need to probe it differentially, or else you'll get that DC offset.

Just because the ibufgds output driving the INTERNAL fpga clock net CLKIN_IBUFGDS_OUT is single ended, does not magically make the EXTERNAL signal (you know, the differential pair clk_p_in/clk_n_in) any different. You can more or less think of that ibufgds buffer as a differential to single ended converter.