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Violation of paths containing adders when doing synthesis in DC

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s8319

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hi all:
Now i doing a synthesis using DC, there are always paths violated,
the paths containing some adders(ADDFHX1,ADDFHX4,ADDFX2 etc.) in smic18 lib whose delay are relatively bigger than other one.
The constrains "set_max_area 0" is added, I donot know what type of these adders are and whether they the fastest ones, should i use "set_implementation" constrain, does it affect?

thank you very much!
 

anjali

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Re: question about DC

based on the path delay constraints, tool will select an adder among ADDFHX1, ADDFHX2......
 

jackson_peng

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question about DC

there are two points which might help you improve your timing.
first, don't use the set_max_area before you do the first rount compile. actuall the timing should be concerned most.

second, go back to rtl to check whethe there do have a path with several ADD operation. if that is the case, modify your coding can greatly improve your timing. (eg: 4 ADD operators can be strutured with a 4-2 compressor and an Adder)

hope that may be help.
 

s8319

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Re: question about DC

Thank you for you suggestion!
I think correct the rtl code is the best but last way to use, as it is too boring.
I want to know how much does the DC synthesis can affect the performance, is it useless to add constrains to optimization, or the effect can be neglected?

thanks
 

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