VHDL, Xilinx Spartan3, errror: unsupported Clock statement

[Gofs]

Hi there,

I am quite new in VHDL and I came from years of programming in 'usual' languages like C++, C# and Pascal so it is difficult for me to understand some things in VHDL and maybe I am doing something stupidly wrong. Well I am trying somehow to do following:

PROCESS_COUNTER: process(CLK, RESET, ClockReset)
begin
if RESET = '0' then
Counter <= (others => '0');
elsif ClockReset'event then
Counter <= (others => '0');
elsif rising_edge(CLK) then
Counter <= Counter + 1;
end if;
end process;

Generally I want to reset the counter when a RESET signal will go 0 or there will be a signal change on ClockReset signal. Apparently this way is not the right way. Can somebody give an idea how to make the code doing that? Thanks.

 

[TrickyDicky]

the standard template for a register with async and synchronous reset is this:

process(clk, reset)
begin
  if reset = '1' then 
    --do async reset here

  elsif rising_edge(clk) then
    if sync_reset = '1' then
      --sync reset here

    else
      --normal logic
    end if;

  end if;
end process;

You cannot reset on a "change" in a "clockreset" because there is no logic that can detect a change directly. You will have to register the ClockReset signal with the clock and then detect changes manually (assuming it is already a synchronous signal). You can then use this change detection as either a sync or async reset.

 

[shaiko]

You basically told your synthesis tool to use a Flip Flop sensitive to 3 different clock edgdes:

1.rising edge of "ClockReset" (because of the 'event attribute).
2.falling edge of "ClockReset" (because of the 'event attribute).
3. rising edge of "CLK".

There's no FPGA logic that can satisfy all 3 of the above. Only the 3rd statement would work - effectively describing a positive edge sensitive D type Flip-Flop.
Remember, you're DESCRIBING DIGITAL LOGIC CIRCUITS - NOT PROGRAMMING.