matrixofdynamism
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I have HDL code for a statemachine type of circuit. I am writing a testbench for it. At the moment I provide it with inputs and than after clk cycle delays use VHDL assert statements on each output of the circuit. This way I have an automatic testbench which shall produce a failure message if any assert statement fails.
However, I think that it would be better if I can actually also read the internal state signal of the circuit in the testbench and use assert statement on that also, this will provide a more complete coverage.
How do I see signals internal to a DUT in a VHDL testbench?
However, I think that it would be better if I can actually also read the internal state signal of the circuit in the testbench and use assert statement on that also, this will provide a more complete coverage.
How do I see signals internal to a DUT in a VHDL testbench?