library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity csa is
generic (
N: integer:=32
);
port(
A : in STD_LOGIC_VECTOR(N-1 downto 0);
B : in STD_LOGIC_VECTOR(N-1 downto 0);
C : in STD_LOGIC_VECTOR(N-1 downto 0);
Z : out STD_LOGIC_VECTOR(N-1 downto 0);
COUT : out STD_LOGIC_VECTOR(N-1 downto 0)
);
end csa;
architecture behavioral of csa is
begin
Z<=((not A) and (not B) and C) or ((not A) and B and (not C)) or (A and (not B) and (not C)) or (A and B and C);
COUT<=(A and B) or (A and C) or (B and C);
end behavioral;