VHDL vs Verilog which more popular?

[AaronDu]

VHDL is more popular than Verilog.
I think that the structure of VHDL is better than Verilog , but Verilog is easier than VHDL , and the user quantity is great than VHDL in my country

 

[juggernaut]

I can't compare VHDL vs Verilog, as I've only ever used VHDL. But as everyone seems to agree, VHDL is the more structured language, and I think that makes it the better language, and in ways that will become more important in the future.

I think that the advantage of a "hardware description language" is to allow us to abstract - to remove ourselves from the tedium of gates and wires and focus on the bigger picture. As designs get more complex and devices get bigger, this becomes increasingly important. Although it's nice to have complete control of every gate and flipflop, as we did when we designed FPGAs with schematic entry tools, it becomes unweildly as designs grow larger.

So I think it best to embrace the 'software' aspects of hardware description languages - to use records, to infer rather than instantiate, to use functions and procedures. This means placing ones faith in the synthesise tools, but I think they do a better job these days than most people let on, and I'm seldom dissapointed.

So why then is VHDL better? Well, a more structured language provides a 'safer', more robust environment for building large, scalable designs - try writing a large program in BASIC and you'll know what I mean.

Just my 2 cents...

 

[kormesii]

VHDL is very easy and popular language, but I think that VHDL doesn't have the powerfull capabilities of Veriolog. While VHDL is fast - to designing the base concepts of design - he is not very convenient for simulation of big projects / the simulation will take a lot of time, resourses and so on/ . I'm sure that Verilog is more powerfull /from design and practice purposes/. The only minus of Verilog is that is not so abstract as VHDL still. But I think that this will be solved soon.

In addition : In my opinion the mixed design /VHDL and Verilog/ is the best for every project.

 

[loci8]

As i started to learn something about chip-development, only VHDL was said to be "good". But i'm from the german-speaking academic area, and not from the industry.
A little company i work on a project now, left it to me, which language to use, because in the company both will be applied.

Nevertheless i have decided to choose VHDL, in my opinion it's really more "tidy" to use for a beginner (like me).

 

[stevepre]

loci8,

You'd better think about that...

Take a look at all the EDA tools. All of them support verilog, and only some of them support VHDL. You can see the majority is verilog. And do you really think the majority are fools?

Verilog is the best choice.

<font size=-1>[ This Message was edited by: stevepre on 2002-04-26 04:33 ]</font>

 

[Hero]

This is truth about VHDL and Verilog.

VHDL and ADA are strictly pascaloid languages used for military projects. VHDL languge is derived from military projects during 80s finansed by DARPA.

In 1987 VHDL is accepted by IEEE as official standard IEEE 1076.

Verilog is not military language and it is accepted in industry as unofficial industrial standard.

As every military thing VHDL is not quite suitable and efficient for small comercial projects.

You can think about VHDL and Verilog as ADA and C++.

 

[chinadicom]

I think compare Verilog and VHDL is just like comparing C and Ada, the former is ease to learn, and the latter is more difficult to learn, but they can do the same thing. In industrial, the Verilog is pop than VHDL. I know Verilog and VHDL, but I like Verilog.

 

[loci8]

@stevepre: Thanks for your message.
I think i have to change the way of thinking about the languages.
But for learning purposes i finnish the current project with VHDL, but in future Verilog will be the better choice.

But its very surprising, that universities in the austrian-german area do so much insist on VHDL, not Verilog.
Maybe this is a good example for the diffrence between university-learning and industry-working :wink:

 

[ptoo30]

I have been working for 30ys at semiconductor area. Most of the customer request VHDL compiler to ASIC libraly. And semiconductor engineers are familiar to verilogHDL. The origin is different, VHDL was initialy developped for making the specification of the system by DOD. Verilog HDL was developped to make ease design for ASIC engineers. So VHDL is formal. As of now there are many code converters between VHDL and verilogHDL, witchever you choose there shall no difficulties tor your development. I
personately like VHDL because system engineers use VHDL.

 

[armer]

vhdl verilog

I with stevepre too, i thank verilog is better for us to design asic chip, verilog is commicial. so many books and material of vhdl is used for education and is spread.

 

[the_penetrator]

i use both languages, started with Verilog which i found far more simple
than VHDL. However VHDL gives more opportunities for compact design, and readability.
On the other hard, practically speaking, Verilog has a much better concept-to-creation time than VHDL. Verilog needs of a learning curve duration of a week for the 80% of the language, in contrast to VHDL which you have to sweat for 2 months and more and get serious knowledge for small projects.

On the synthesis path, VHDL is not that bad. It might have a slight disadvantage to Verilog, again it is due to the fact that Verilog was developed by vendors (Cad*nc*) and on the other side, VHDL as a military recommendation for documenting digital (or more general) systems. Practice vs formality, i can say...

They are both here to stay for many years, together with a third language (C++ for hardware, SystemC, Superlog, Vera i don't know whioch one...)

pene

 

[buzkiller]

Verilog is more popular for ASIC , VHDL for FPGA.

regards,
Buzkiller.

 

[ultraunix]

Hi, I worked with both these languages.
I started (5 years ago) with verilog. Verilog is veri easy to learn.
Now I´m using VHDL. Whith VHDL ,for me, is easier to manage large project (developed by more than 1 person), and is more difficoult to insert erros in the code. VHDL is also enough powerful for the develop of the test-bench. As far as I know VHDL is more used in Europe, Verilog in the U.S.A.

 

[lipton]

Verilog is more popular in England and both Americas, VHDL is more popular in continental Europe and Japan.

 

[steshenko]

:? IMHO I come to FPGA design from discrete digital design - i use Verilog more often than VHDL, Verilog like C - simple syntax
My coalegue programmers use VHDL - good structure and other ADA benefits

 

[asicplace]

The answer depends on several factors and seems to be segmented by industry and geography. In the US, military and telecom generally use vhdl. Commercial asic designers mostly use verilog. Northern Europe is mainly vhdl as well. You can go to www.deepchip.com to get a lot more detailed answer, including details from the 2002 Design Automation Conference...

 

[nitr8]

well the future is for verilog. Since Accellera (**broken link removed**) the standardizing body of vhdl and verilog has standardized an new language based on verilog called systemverilog(**broken link removed**) . Accellera has no plans for improving VHDL. Systemverilog will even have "sugar" as the verification language.

 

[f117]

I think there're few difference between Verilog and VHDL in essence. They are both hardware description languages, witchever you choose there shall no difficulties tor your development.

I don't think either of them is more difficult to learn, they are both easy to learn. I don't think "system engineers use VHDL". They are neither suit for system engineers. The true thing is SystemC or other C-kind description languages

I started with VHDL. Later I found sometimes Verilog is more powerful. So I started to learn Verilog. Now I used both of them, but prefered Verilog to VHDL.

It can only say: "Verilog is more popular for ASIC , VHDL for FPGA"

 

[andromeda]

One citation from famous Janic Bergeron's book (Writing Testbenches: Functional Verification of HDL models):
"... both languages are inadequate by themselves, especially for verification. They are both equally poor for synthesizeable desription. ... The right question should be "Which one do I hate the least?" And the answer to that question is: "the one I'm not currently working with". "

My own expirience is:
1. simulation in Verilog is much faster than simulation in VHDL - it is especially important for post-synthesis simulation - of course we can write code in VHDL and generate post-synthesis netlist in Verilog
2. development of synthesisable code in Verilog is much faster then in VHDL - for any project size
3. development of verification environment in Verilog is faster then in VHDL
if we develop syntesizable testbench for emulation purpose - we must do that in Verilog or VHDL
if we build verification environment which don't need to be synthesisable - we can do that much faster using Vericity Specman and e

In Europe, almost only VHDL is used.
In US, Verilog is more dominant.

 

[nitr8]

Look at the new SystemVerilog 3.0 standard. and u will realize that the problem of both being bad in verification doesn't apply to systemVerilog 3.0 any more.

YES it is the new HDL standard.