VHDL vs Verilog which more popular?

[jako123]

i prefer

VHDL

of course

reason: I'm more familiar with it


ciao

 

[killbuz]

in my university they teach verilog because its easy.
and my research work needs VHDL.So better know both.Or make ur designs a mixed one.

 

[pcking1972]

just verilog.

 

[Zerox100]

VHDL and Verilog both are popular. VHDL has more high level construct. verilog has more low level construct. depend on your goal one of them is best. But VHDL often used in more complex system design.

 

[dspusr]

**broken link removed**

i don't like VHDL too.

 

[leonqin]

I don't think so.
The future belongs to neither vhdl nor verilog.

 

[radix]

VHDL, the new Latin

Here's another viewpoint. I got the email directly from the ESNUG mailing list. I looked for it on www.deepchip.com so that I could just post a link, but I don't think John has posted it on his web page yet.

Radix


!!! "It's not a BUG, jcooley@TheWorld.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / INDUSTRY GADFLY: "VHDL, the new Latin"
_] [_
by John Cooley, EE Times Columnist

Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222

When Synopsys CEO Aart De Geus stood up to give his key-note address
at DVcon'03, nobody expected him to say anything controversial. It's
not his style. So when he gave a talk on the history of the
productivity gap in EDA for the past 20 years, we all thought that
everything was normal.

But subtly, during that talk, Aart put up three slides that showed
Verilog and VHDL as being what's here now, with only System Verilog
being in the future. His final slide had an overlay stating that
System Verilog is 100 percent backward-compatible with Verilog and
that it thus will succeed because it will let you keep all your old
Verilog legacy code. Aart closed his speech by stating that Synopsys
is committed to developing System Verilog synthesis, simulation and
analysis tools.

It was as if a smart bomb had hit the room. The trade press and Wall
Street weenies considered the comments no more than a pitch for
System Verilog. But my fellow chip designers clearly saw the writing
that Aart had put up on the wall. Verilog and VHDL may be here now,
but in the future only a flavor of Verilog will be left.

"I think Aart just said that VHDL is dead," Cliff Cummings of
Sunburst Designs, said to me in the awkward 30 seconds that followed
Aart's speech. "At least, that's what I think he said." Consultant
Stu Sutherland agreed with Cliff. "He said VHDL has no future. That
sounds pretty dead to me." Then Dan Joyce and two of his co-workers
from Hewlett-Packard walked up and asked if Aart had just agreed with
Joe. (Back in the 1995 OVI conference keynote address, Joe Costello,
then the CEO of Cadence, had said that "VHDL was a $400 million
mistake.")

In the confusion, I got picked to approach Aart and ask him exactly
what he was saying about VHDL.

Aart replied that his R&D group wasn't developing any new VHDL-based
tools, but he also said it will take years to phase out VHDL because
leaving customers in the lurch would be bad form. In short, he
wasn't abandoning VHDL as much as promoting System Verilog. "This is
a big statement. We are putting the Synopsys weight behind this
language for RTL plus design," said Aart. "I do believe in the long
term, though, that System Verilog will be the dominant language."

So after years of the Verilog vs. VHDL wars, in one speech, Aart had
kicked VHDL out of the big-money ASIC flows. And VHDL was now the
new Latin; a dead language supported only by a few obscure holdouts
in the small-money FPGA world. Verilog (err -- make that a beefed-up
Verilog) had won.

-----

John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a
contract ASIC designer, and loves hearing from engineers at
"jcooley@TheWorld.com" or (508) 429-4357.

 

[womiga]

verilog is popular in future.

 

[calvinhorng]

Folks:


read the article in the following link
and that shall be the synopsis' viewpoint

**broken link removed**

 

[ddt694]

all stupid tools!

i think altera's AHDL is the right one.

but, of course, it is not the industry
standard.

 

[leon]

verilog is a powerful language which can povide model at gate level.
In Asic design, the verilog is used popular.
In FPGA design, both them are used popula.

 

[maestor]

I found this interesting site:

VHDL & Verilog Compared & Contrasted
Plus Modeled Example Written in
VHDL, Verilog and C

http://www.parmita.com/verilogcenter/verilogvhdl.html

Regards,
Maestor

 

[stewmal]

I believe that the big EDA companies will lead the push to make Verilog the industry choice. They may support VHDL, but Verilog will be pushed.

 

[qlyus]

It seems people use VHDL more than Verilog in FPGA/PLD design of embedded system. But Verilog dorminates in ASIC designs. As a matter of fact, I've never seen VHDL in ASIC design at least in the valley.

I persnally learnt and used VHDL first, then switched to Verilog (required by ASIC company), and am not willing to use VHDL again.

 

[flatulent]

ocean based

I heard a report that countries around the Atlantic Ocean use one of these and those around the Pacific Ocean use the other. The US which is on both have the section of the country against each ocean using that type.

 

[srirams77]

most indian companies use Verilog.

 

[maniasonic]

of course verilog. vhdl is so dogmatic that is not friendly to engineers.

 

[AlexWan]

Re: VHDL, the new Latin

said Aart. "I do believe in the long
term, though, that System Verilog will be the dominant language."

For that, if do the designers need to know about the bottom of IC? On the other side, when we design a chip with the higher level language, how do we ensure the area, power, timing etc. of this chip?

 

[cloudsuns]

vhdl is more popular than verilog
but i think verilog will overpass vhdl

 

[z81203]

ooh,

verilog is from industry.
vhdl is from government.