I can't compare VHDL vs Verilog, as I've only ever used VHDL. But as everyone seems to agree, VHDL is the more structured language, and I think that makes it the better language, and in ways that will become more important in the future.
I think that the advantage of a "hardware description language" is to allow us to abstract - to remove ourselves from the tedium of gates and wires and focus on the bigger picture. As designs get more complex and devices get bigger, this becomes increasingly important. Although it's nice to have complete control of every gate and flipflop, as we did when we designed FPGAs with schematic entry tools, it becomes unweildly as designs grow larger.
So I think it best to embrace the 'software' aspects of hardware description languages - to use records, to infer rather than instantiate, to use functions and procedures. This means placing ones faith in the synthesise tools, but I think they do a better job these days than most people let on, and I'm seldom dissapointed.
So why then is VHDL better? Well, a more structured language provides a 'safer', more robust environment for building large, scalable designs - try writing a large program in BASIC and you'll know what I mean.
Just my 2 cents...