VHDL vs Verilog which more popular?

[KamenRider]

I prefer Verilog myself. But itt seems to me that it is a tie in the industry. A lot of IP cores and papers provide both sources.

 

[cikyen]

I like VHDL batter.

 

[easetv]

Personally I like Verilog more.
Both HDL used in my company, some old IPs are written in VHDL, but all new design in Verilog.

 

[edacw1]

I think Verilog is more popular.

 

[sibuku]

systemverilog will kill VHDL.
Although I use vhdl now.
I recommend you use verilog2001 than systemverilog

 

[sunlight]

I read all the comments just now.
A very interesting topic.
hmm.... I use vhdl more often, but it doesn't mean I like it.

 

[roger]

There are future version of Verilog , Verilog2000 systemVerilog
but no VHDL, so Verilog is going to dominate the future HDL world.

 

[gentle_man]

I prefer verilog because it's easy

 

[pci1000]

i think verilog is much better,
because every engineer had studied c language and verilog is like c
so it is should be more easier than vhdl

 

[bittware]

I prefer VHDL

 

[jelydonut]

I don't understand how someone who would know both Verilog and VHDL could perfer to use VHDL.. Too much typing for the same crap..

I love that instantiation idea that systemverilog has.. how can you go wrong with..
blah blah(
.*(*)
);

jelydonut

 

[richie]

Verilog is prefered.

 

[computer_terminator]

I used VHDL in an Europe company, used verilog in an US company.
In my point of view, to write the design with VHDL, and models with verilog.

 

[shengkaiyi]

I vote to verilog. Verilog is very like c language and is more flexiable than vhdl; while vhdl has a strict, good structure. I prefer to verilog and my colleages are using verilog.