VHDL verilog mixed simulation and synthesis

[casual3_2002]

Can anyone post some links to the mixed mode VHDL/verilog simulation and synthesis documents? I need to use a VHDL IP in a verilog environment, I'd like to know how to instantiate the VHDL IP in our verilog code for simulation and synthesis. Thanks a lot!

 

[wadaye]

Hi casual3_2002,

You can just instantiate the VHDL IP in our verilog code as same as your Verilog

Module, there is no difference in the verilog code which instantiate it. The only

difference is that you should use "read_hdl -format vhdl"(something like this) to read

them into the tool.

 

[deva_eda]

vhdl instantiation in verilog is same as instantiating verilog modules same port mapping and parameter mapping.

Just check if your simulation and synthesis tool support mixed designs