Feb 7, 2015 #1 ivlsi Advanced Member level 3 Joined Feb 17, 2012 Messages 883 Helped 17 Reputation 32 Reaction score 16 Trophy points 1,298 Activity points 6,868 Hi All, How to pass Parameters from VHDL to Verilog? Thank you!
Feb 7, 2015 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,410 Helped 14,749 Reputation 29,780 Reaction score 14,095 Trophy points 1,393 Location Bochum, Germany Activity points 298,054 As you would do in pure VHDL. VHDL generics translate to Verilog parameters.