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VHDL Type duplicate definition in different file, won't connect?

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legendbb

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Dear Experts,

I have some unique data type used through my project.

In order to make some IP source file independent of the common package.

I redefined TYPEs in local package with the identical text.
Code:
TYPE MY_Array IS ARRAY (0 TO 2) OF STD_LOGIC_VECTOR(3 DOWNTO 0)

Back in integration, receive error from Vivado, expected MY_Array.

I understand, there are two definitions of the "MY_Array", but I just don't want to reference the common package.

What's the right way of doing this, give the fact I have to use my data type.

Thanks,
 

K-J

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In order to make some IP source file independent of the common package.
This doesn't make any sense and is the root cause of your problem. You create a package so that it can be commonly used.

I redefined TYPEs in local package with the identical text.
Code:
TYPE MY_Array IS ARRAY (0 TO 2) OF STD_LOGIC_VECTOR(3 DOWNTO 0)

Back in integration, receive error from Vivado, expected MY_Array.

I understand, there are two definitions of the "MY_Array", but I just don't want to reference the common package.
I suggest you get over your not wanting to reference the common package. You haven't given any reason for this want.

What's the right way of doing this, give the fact I have to use my data type.
The right way is to define the type once in a package and then use the package, end of story.

Kevin Jennings

Thanks,
 

legendbb

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Thanks for being straight. I understand the rule back from school. But never tested in real design. Now it bites. I will switch back to common package.
 

TrickyDicky

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This comes about because you have used the same name in two packages. A local type declaration will override anything included in packages, unless you specifically ask for the "other" one.
To differentiate and make this error go away, when you include the same type from two different packages, you need to specify which one you mean:

signal a : package1.my_array;
signal b : package2.my_array;

But remember, the are different types, so the following would be illegal:

a <= b;
 

legendbb

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Indeed, VHDL is very type safe.
 

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