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VHDL testbench SDF file annotation problem

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jocelyn97

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Hello,
I‘m trying to measure the power consumption of my design. I have synthesized the files and created the SDF file using DC.
When I'm trying to do the Gate-level simulation using VCS and annotate the SDF file to a VHDL testbench, I get the following errors:

Code:
Error-[IACSTC] Sdf-Annotate Failed
  Incorrect argument passed to -sdf switch:
  'typ:tb_p2/uut:/home/xfeng/linh_prjs/PRESENT/dc/mapped/Cipher.sdf'.
  Correct Usage : (min/typ/max):scope_name:sdf_filename.
  Please check if 'scope_name' is set correctly.

I use the command:
-sdf typ:tb_p2/uut:/home/xfeng/linh_prjs/PRESENT/dc/mapped/Cipher.sdf

This is my makefile:

Code:
.PHONY: vcs sim verdi clean
all:vcs sim verdi
    
OUTPUT   = simv
ALL_DEFINE = +define+NETLIST_SIM
VPD_NAME = +vpdfile+${OUTPUT}.vpd
##========== code coverage command =======
CM_NAME  = -cm_name ${OUTPUT}
CM_DIR   = -cm_dir ./${OUTPUT}.vdb
CM       = -cm line+cond+fsm+branch+tgl
#netlist-sim lib
LIB_NET_FILE = -v /home/xfeng/library/tsmc90/tsmc90/tsmc090.v
##======================================
anvlog:
    vlogan -sverilog -nc +v2k -kdb -f verilog_filelist.f

anvhdl:
    vhdlan -smart_order -full64  -nc -no_opt -f vhdl_filelist.f

vcs:
    vcs  \
              -timescale=1ns/1ns      \
              -full64 +v2k  \
              -fsdb          \
              -l vcs.log     \
              +neg_tchk \
              -negdelay     \
                  -sdf typ:tb_p2/uut:/home/xfeng/linh_prjs/PRESENT/dc/mapped/Cipher.sdf   \
              +no_notifier  \
              -o ${OUTPUT}   \
              -kdb -debug_access+all -lca   \
              ${CM}          \
              ${CM_NAME}     \
              ${CM_DIR}      \
              ${VPD_NAME}   \
              ${ALL_DEFINE} \
              +libext+.v+.V${LIB_NET_FILE}
sim:
    ./${OUTPUT}    \
    -ucli -i wave_gen.tcl \
    -l sim.log     \
     ${CM}         \
     ${CM_NAME}     \
     ${CM_DIR}      \
     ${VPD_NAME}   
#show the coverage
dve_cov:
    dve -covdir *.vdb &
urg:
    urg -dir *.vdb -report urgReport
dve:
    dve -vpd  ${OUTPUT}.vpd  &
verdi_cov:
    verdi  -cov -covdir *.vdb &
verdi:
    verdi -f ../filelist.f -sv -ssf testbench.fsdb &
verdi_new:
    verdi -elab simv.daidir/kdb  &
clean:
     rm  -rf  *~  core  csrc  simv*  vc_hdrs.h  ucli.key  urg* *.log  novas.* *.fsdb* verdiLog  64* DVEfiles *.vpd *.dat vdCovLog

This is my testbench file:

Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- file functions
USE ieee.std_logic_textio.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
USE STD.ENV.ALL;
 
ENTITY tb_p2 IS
END tb_p2;
 
ARCHITECTURE bench OF tb_p2 IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Cipher
    Port ( clk      : in  STD_LOGIC;
           nReset   : in  STD_LOGIC;
             dataIn1  : in  STD_LOGIC_VECTOR (3 downto 0);
           dataIn2  : in  STD_LOGIC_VECTOR (3 downto 0);

              key      : in  STD_LOGIC_VECTOR (3 downto 0);
           dataOut1 : out STD_LOGIC_VECTOR (3 downto 0);
           dataOut2 : out STD_LOGIC_VECTOR (3 downto 0);

           done     : out STD_LOGIC);
    END COMPONENT;
 

   --Inputs
   signal clk    : std_logic := '0';
   signal nReset : std_logic := '0';
   signal dataIn1 : std_logic_vector(3 downto 0) := (others => '0');
   signal dataIn2 : std_logic_vector(3 downto 0) := (others => '0');

   signal key     : std_logic_vector(3 downto 0) := (others => '0');
  
    --Outputs
   signal dataOut1 : std_logic_vector(3 downto 0);
   signal dataOut2 : std_logic_vector(3 downto 0);

   signal done : std_logic;

   signal plaintext : std_logic_vector(3 downto 0)  := (others => '0');
   signal md1 : std_logic_vector(3 downto 0)  := (others => '0');
   signal md2 : std_logic_vector(3 downto 0)  := (others => '0');
  
   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
 
BEGIN
 
  dataIn1 <= plaintext XOR md1;
  dataIn2 <= md1;

 
  -- Instantiate the Unit Under Test (UUT)
   uut: Cipher
    PORT MAP (
              clk => clk,
              nReset => nReset,
              dataIn1 => dataIn1,
              dataIn2 => dataIn2,

              key => key,
                dataOut1 => dataOut1,
                dataOut2 => dataOut2,

              done => done
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
    
    -- mixed (event-driven/cycle-based) result check
    check_results : process
    
        variable lineIn            : line;
        variable good_number        : boolean;
        variable space                : character;
        variable tv_key            : std_logic_vector( 79 downto 0);
        variable tv_plaintext    : std_logic_vector( 63 downto 0);
        variable tv_md1            : std_logic_vector( 63 downto 0);
        variable tv_md2            : std_logic_vector( 63 downto 0);
        variable tv_mk1            : std_logic_vector( 79 downto 0);--for dummy purposes due to tv-file format
        variable tv_mk2            : std_logic_vector( 79 downto 0);--for dummy purposes due to tv-file format
        variable tv_ciphertext    : std_logic_vector( 63 downto 0);
        variable out_temp           : std_logic_vector( 63 downto 0);
        
        variable tv_plaintext_chunk  : std_logic_vector(3 downto 0);
        variable tv_md1_chunk          : std_logic_vector(3 downto 0);
        variable tv_md2_chunk          : std_logic_vector(3 downto 0);
        variable tv_key_chunk          : std_logic_vector(3 downto 0);
        variable tv_ciphertext_chunk : std_logic_vector(3 downto 0);
        

-- these files only have 10 random test vectors
        file vector_file_SPS: text open read_mode is "/home/xfeng/linh_prjs/PRESENT/TestBench/tv_sPS_10.txt";
---------------------------------------------------------------------------------------------
--        reference to these files from the root directory of your modelsim library,
--        e.g. c:\Modeltech_pe_edu_10.1\examples (just copy it there)
---------------------------------------------------------------------------------------------
        
        procedure assertMatch(testResult, correctResult : in std_logic_vector) is
            variable msg : line;
            variable msg2 : line;
        begin

            if (testResult'length mod 8 = 0) then
                hwrite(msg, testResult);
                write (msg, string'(" should be "));
                hwrite(msg, correctResult);
            else
                write(msg, testResult);
                write(msg, string'(" should be "));
                write(msg, correctResult);
            end if;

            write (msg2, string'("correct result"));

            assert (testResult = correctResult)  report msg.all severity error;
            assert (testResult /= correctResult) report msg2.all severity warning;

        end procedure assertMatch;

        

---------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXX Start of CORE 2 XXXXXXXXXXXXXXXXX
---------------------------------------------------------------------------------------------

        procedure testCipherCore2 (tv_key, tv_plain, tv_out : std_logic_vector) is

        begin
            
            report "---------- Test core 2: shared ----------";
            -- start cipher with new input
            nReset <= '0';
           wait for 1*clk_period;
            
-- load 16 MSB of key
            FOR i in 0 to 3 loop
                tv_key_chunk := tv_key(79-i*4 downto 76-i*4);
                
                key <= tv_key_chunk;
                
                -- wait one cycle to load data
                wait for clk_period;
            end loop;

-- load plaintext, expected ciphertext, and remaining 63 bits of key
            FOR i in 0 to 15 loop
                tv_key_chunk := tv_key(63-i*4 downto 60-i*4);
                tv_plaintext_chunk := tv_plaintext(63-i*4 downto 60-i*4);
                tv_md1_chunk := tv_md1(63-i*4 downto 60-i*4);
                tv_md2_chunk := tv_md2(63-i*4 downto 60-i*4);
                tv_ciphertext_chunk := tv_ciphertext(63-i*4 downto 60-i*4);
                
                plaintext <= tv_plaintext_chunk;
                key <= tv_key_chunk;
                md1 <= tv_md1_chunk;
                md2 <= tv_md2_chunk;
              
                -- wait one cycle to load data
                wait for clk_period;
            end loop;
                
            nReset <= '1';


            -- wait for cipher to finish
            wait until done = '1';
            wait for clk_period;
            
            FOR i in 0 to 15 loop
            out_temp(63-i*4 downto 60-i*4) := dataOut1 XOR dataOut2;
            -- wait one cycle to load data
            wait for clk_period;
            end loop;
            
            -- test result
            assertMatch(out_temp,tv_out);
            -- wait one cycle before next (possible) reset
            wait for clk_period;
            
            report "---------- core 2: shared successfully tested! ----------";
            
    
        end procedure testCipherCore2;
---------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXX End of CORE 2 XXXXXXXXXXXXXXXXX
---------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXX TESTING STARTS  XXXXXXXXXXXXXXXXX
---------------------------------------------------------------------------------------------

    begin
        -- system init
        wait for 1.5*clk_period;

---------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXX READ IN FROM FILE tv_sPS_10.txt XXXXXXXXXXXXXXXXX
---------------------------------------------------------------------------------------------

report "---------- Test using testvector file tv_sPS_10.txt----------";
        read_loop_SPS: while not endfile(vector_file_SPS) loop
            readline(vector_file_SPS, lineIn);
            next when (lineIn(lineIn'left) = '-'); -- comment line
            
            -- read key
            hread(lineIn, tv_key, good => good_number);
            assert (good_number) report "Incorrect test vector format (key)" severity error;
            -- read space character
            read(lineIn, space);
                        
            --for dummy purposes due to tv-file format
            -- read key mask mk1,
            hread(lineIn, tv_mk1, good => good_number);
            assert (good_number) report "Incorrect test vector format (mk1)" severity error;
            -- read space character
            read(lineIn, space);
            --for dummy purposes due to tv-file format
            -- read key mask mk2
            hread(lineIn, tv_mk2, good => good_number);
            assert (good_number) report "Incorrect test vector format (mk2)" severity error;
            -- read space character
            read(lineIn, space);
            
            -- read plaintext
            hread(lineIn, tv_plaintext, good => good_number);
            assert (good_number) report "Incorrect test vector format (plaintext)" severity error;
            -- read space character
            read(lineIn, space);
            
            -- read plaintext mask md1
            hread(lineIn, tv_md1, good => good_number);
            assert (good_number) report "Incorrect test vector format (md1)" severity error;
            -- read space character
            read(lineIn, space);
            
            -- read plaintext mask md2
            hread(lineIn, tv_md2, good => good_number);
            assert (good_number) report "Incorrect test vector format (md2)" severity error;
            -- read space character
            read(lineIn, space);
            
            -- read ciphertext
            hread(lineIn, tv_ciphertext, good => good_number);
            assert (good_number) report "Incorrect test vector format (ciphertext)" severity error;
            -- read space character
        
---------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXX TEST core 2 SHARED PRESENT XXXXXXXXXXXXXXXXX
---------------------------------------------------------------------------------------------
            testCipherCore2(tv_key, tv_plaintext, tv_ciphertext);

        end loop read_loop_SPS;
        report "---------- End of testvector file tv_SPS_10.txt----------";


    report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! Ende!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!";
        wait;
    end process check_results;   
    


END;


This is my SDF file:

Code:
(DELAYFILE
(SDFVERSION "OVI 2.1")
(DESIGN "Cipher")
(DATE "Tue Sep 13 16:34:29 2022")
(VENDOR "typical")
(PROGRAM "Synopsys Design Compiler cmos")
(VERSION "O-2018.06-SP1")
(DIVIDER /)
(VOLTAGE 1.00:1.00:1.00)
(PROCESS "typical")
(TEMPERATURE 25.00:25.00:25.00)
(TIMESCALE 1ns)
(CELL
  (CELLTYPE "Cipher")
  (INSTANCE)
  (DELAY
    (ABSOLUTE
    (INTERCONNECT stateFF/state/gff_16/SFF_3/Cell_reg/Q U9/A (0.000:0.000:0.000))
    (INTERCONNECT keyFF/keystate/gff_20/SFF_3/Cell_reg/Q U9/B (0.000:0.000:0.000))
    
         ………

So how to do the Gate-level simulation using VCS with VHDL testbench?
I would be very grateful if you could give me a little advice.

Thank you so much!
Jocelyn.
 

well the error message seems clear, hope your try more than one time...
 

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