vhdl testbench assert question

[hithesh123]

In my testbench, I am writing data to one of the registers in the UUT.
The UUT is a SPI slave.
How do I check if the data is being written to that register using assert.
The testbench generates only SPI signals.

I can see in the simulation that data is being written to that register, but how do I check using assert.
I am using ISE 13.6 for simulation.

 

[imbichie]

which language you are using?
in verilog/system-verilog you can use the hierarchical dot operator " . ", for getting the registers or signals in the testbench.
In vhdl also you can use the hierarchical operator, i dont remember whether its dot " . " or slash " / "

 

[TrickyDicky]

You need to use VHDL 2008 to get access to signals/variables via the heirachy. Otherwise you have to route the signal into your testbench to access it.

 

[hithesh123]

I am using VHDL.
How do I find out if I am using VHDL 2008 or a previous version?

 

[TrickyDicky]

That would be your coding style - there are new features to the language that you need to include in your code. Doulos has a great guide to the new 2008 features: https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/
You then need a simulator that supports them, and I doubt the ISE simulator does. You would need a full featured simulator like modelsim.

 

[ads-ee]

ISE doesn't support even 1076-2002, let alone 2008.

I think it supports VHDL '93 and Verilog 2001.

Good reason to consider Altera if you can't get Modelsim/Aldec/Incisive/VCS/etc

regards

 

[TrickyDicky]

If you wanted modelsim, you can download the free version of modelsim from altera. Its a fairly recent version with VHDL 2008 support. You can easily map in all the xilinx libraries and use it as your simulator.

 

[hithesh123]

I have used modelsim before. I was able to probe the signals.
But same feature is not available in ISE sim.

 

[K-J]

In my testbench, I am writing data to one of the registers in the UUT.
The UUT is a SPI slave.
How do I check if the data is being written to that register using assert.
The testbench generates only SPI signals.

I can see in the simulation that data is being written to that register, but how do I check using assert.
I am using ISE 13.6 for simulation.

- If the register can be read back, then read it back and add the assertion there.
- If writing to the register causes some other top level signals to change to a known state, then you can check for the proper response. For example, if writing to register X with value Y should cause the top level signals XYZ(3:0) on the UUT to go to '1001', then after you complete the SPI write, you would assert that signal XYZ is indeed '1001'.