Yes, very confusing post.
There are ways to access lower-level signals, for example:
https://www.doulos.com/knowhow/vhdl/vhdl-2008-easier-to-use/#hierarchicalnames
Also, you can just bring out signals in your ActiveHDL waveform and manually stimulate them.
But, I have to ask: if you want to stimulate a lower-level module, why aren’t you using a test bench for THAT module?
So, in my project (DUT) we have a down-path and a up-path.
Currently we send specific data (read from a file) as an input to the down-path and we send random data as an input to the up-path.
The problem is that the random data being generated for the up-path didn't quite match a real case scenario so my job now is to fix that.
We came to the conclusion that the input of the up-path should be selected from the input of the down-path (which is read from a file) and not being random.
There is a block inside the DUT that has interfaces on both down-path and up-path and this block stores the down-path data. So I can select the data I want to use as an input to the up-path.
This block is the top hierarchy of 3 others blocks (one that splits the data, one that stores the data and one that chooses the flow of the data).
I want to access those 3 blocks, but from my main TB.vhd file I wasn't able to do it.
I'll check the link you sent me and I'll try some stuff out then I'll let you know if I was able to do it.
Quick noob question if you have the time and patient to answer:
On the TB when I add an component, let's say (block_demux_rd), it will initialize that components RTL (ports and architecture) right?
All I can do is, knowing the blocks ports and architecture from the rtl, stimulate it right?