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[SOLVED] VHDL Test Bench - Beginner

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kemalkemal

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I use quartus ii and model sim altera se.
When i write a test bench file it consists of some code lines related to timing. Than when i compile it and run simulation does this substitute a timing simulation ?
Or do i have to involve .sdo file into the simulation in all conditions for a timing simulation?

For example what kind of simulation is there in this video
Timing or functional ?
This sim issue and test benches confuses me a lot. i appreciate it if you help me to clear my mind.
 

sharath666

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This is not timing simulation. Timing simulation is when your actual gate,net and wire delays are realized in hardware. So you will need a placed and routed netlist with something like a delay file to mimic that. Moreover the delays you are showing us are in the testbench...
 

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In your case you are doing a functional simulation.

Timing delays in a testbench are usually put in by people who get confused when the signals transition in a functional simulation at the same time the clock does. This is done a lot by inexperienced engineers that don't understand the simulation delta cycle and their simulation stimulus isn't working correctly due to delta time problems in the testbench code. I've seen this type of problem caused by badly written clock generation and distribution in the testbench.

The other times I've seen this done in a testbench is to emulate real delays that a bus functional model requires to accurately represent a hardware device.
 

kemalkemal

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is there a link that you could send for timing simulation and test bench.
 

kemalkemal

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I made it with the help of this command line in modelsim. vsim -sdftyp /tbreg4/dut=reg4_vhd.sdo tbreg4 (dut is the name of component in the test benc file)
But note that at my first attempt i receive lots of vsim-SDF-3250 errors. I have overcome it by using component instantiation instead of entity instantiation in the test bench file.
 

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