rtarbell
Member level 2
I am new to VHDL, and I understand that not all VHDL code examples are synthesizable into an actual working circuit. In my first project, my goal is to ultimately download the working code into a (cheap) FPGA just to get my hands dirty with the entire process.
Is there a list of commands that I should not use because they are not synthesizable? I don't exacly know how to pick out the commands that will result in a circuit, and the ones that are in VHDL simply to act as models. For instance, in my current code, I use lots of IF THEN statements, and I don't have a clock at all (do I need one, or can I make one using delay statements like "after"?).
Thank you!
-RT
P.S. I'm using Quartus II free edition from Alera.
Is there a list of commands that I should not use because they are not synthesizable? I don't exacly know how to pick out the commands that will result in a circuit, and the ones that are in VHDL simply to act as models. For instance, in my current code, I use lots of IF THEN statements, and I don't have a clock at all (do I need one, or can I make one using delay statements like "after"?).
Thank you!
-RT
P.S. I'm using Quartus II free edition from Alera.