VHDL synthesizable models

[rtarbell]

I am new to VHDL, and I understand that not all VHDL code examples are synthesizable into an actual working circuit. In my first project, my goal is to ultimately download the working code into a (cheap) FPGA just to get my hands dirty with the entire process.

Is there a list of commands that I should not use because they are not synthesizable? I don't exacly know how to pick out the commands that will result in a circuit, and the ones that are in VHDL simply to act as models. For instance, in my current code, I use lots of IF THEN statements, and I don't have a clock at all (do I need one, or can I make one using delay statements like "after"?).

Thank you!
-RT

P.S. I'm using Quartus II free edition from Alera.

 

[yasser_shoukry]

To write a synthesizable VHDL code you have to write the RTL description (RTL= Register Transfer Level)

In this level your code must take care that your code will be divided into some combinational processes and others are synchronous sequential processes.

i.e each "process" will be interpretered to either a combinational circuit or to some registers and Flip Flops.

To make a "Process" interpreterd as a "Combinational Circuit"
1- All signals in the sensitivity list must be level triggered not edge triggered.
2-For "IF & Case" statements all combiantions must be covered.
3-No "Wait" statements.

To make a "Process" interpretered as a "Synchronous Sequentail" Circuit:
1-Sensitivity list must be senstitve to the edges of the clock and reset signal.
2-All registers and flip flops must be synchronous to the same register.
3-All registers must have a reset value.

If your process does not satisfy either the "Combinational" or "Sequential" circuits , an "Asynchronous Latch" will be inferred. This can ruin your design so you must check the synthesis report.

Good Luck

Added after 1 hours 2 minutes:

I have forgotten to add that XST help (If you are using Xilinx tools) has a lot of synthesizable models for the most used digital components (State m/cs, RAMs, ROMs, Regsiters, ..........)

 

[baonguyenpro]

Having a good book for you: "HDL Chip Design"
You can download in forum: "EDA E-books Upload/Download"

 

[hamadeh]

Take a look at Xilinx Synthesis and Verification Design Guide: **broken link removed**

In chapter 3 :General HDL Coding Styles, section :Coding for Synthesis (page 60).

 

[haneet]

first of all IF-ELSE can be synthesized.
Mostly synthesizability depends on the tools but there are a few which are not synthesizable by any tool.
All the delay instructions i.e "after", inertial delay, etc... are not synthesizable.

 

[Iouri]

quartus is comming with tutorial, try to execute them first. then on the altera web site there is app note HDL coding style, try to use this on when you write yout code, and get youself good VHDL reference book

good lack