VHDL Synthesis Code help ,required clarification.

[Y.SAI SARASWATHI]

Hello,
I am working on a project related to implementation on FPGA using VHDL coding. At first i do not know that real data type will not work for synthesis.
Now I need to perform a function like Y=(a1*x1+a2*x1+.........+a8*x8) where (a1,a2....) and (x1,x2,....) are real numbers(with decimal point) using xilinks ise tool and have to implement it on FPGA are there any other ways.
Please reply me as soon as possible.
Thank you.

 

[ads-ee]

real numbers(with decimal point) using xilinks ise tool and have to implement it on FPGA are there any other ways.

Fixed point with proper scaling of values.

Of course with you, this same topic of scaling fixed point values keeps coming up:
https://www.edaboard.com/threads/321590/
https://www.edaboard.com/threads/321672/

So I expect you'll be finding yourself in more critical situations that require our immediate help...

Please reply me as soon as possible.

I find these types of statements rather irritating...it's like you expect forum members to drop everything and immediately respond to your perceived crisis.

 

[Y.SAI SARASWATHI]

Sorry, that I have mentioned in that way.
But why I have mentioned is , even for the last two posts I could not find any relevant reply.
I will not repeat it again.

 

[TrickyDicky]

You need for formulate your questions properly.
Do you want fixed point or floating point?

floating point will use large amount of logic and have a large pipeline delay
fixed point will use little logic and smaller pipe delay, but you need to ensure the bit depth is ok and acceptible for the accuracy you require.

So, ask a better question, ge a better answer.

 

[Y.SAI SARASWATHI]

You need for formulate your questions properly.
Do you want fixed point or floating point?

floating point will use large amount of logic and have a large pipeline delay
fixed point will use little logic and smaller pipe delay, but you need to ensure the bit depth is ok and acceptible for the accuracy you require.

So, ask a better question, ge a better answer.

I require fixed point logic,actually I am new to work with FPGA's.
Are there any Packages related to synthesis in xilinks ise, so that we can directly work with fixed point numbers
Thank you,

 

[TrickyDicky]

Here is another conflicting statement - first you say fixed, and then you say floating.

You can do either in an FPGA.
Fixed point is easy, as it's really just integers. Floating requires knitting IP cores together

- - - Updated - - -

Like I said, as fixed point is really just integers, there are no special IP cores needed, you can just write:

a <= b + c;
etc.

As you were using real type previously, I get the feeling other things are going to be fundamentally wrong with any code you write at the moment, but you can get vhdl '93 compatible versions of the 2008 vhdl fixed point packages from here:
www.vhdl.org/fphdl

But you can do all you need with the numeric_std libraries (though it involves more typing).

 

[K-J]

I require fixed point logic,actually I am new to work with FPGA's.
Are there any Packages related to synthesis in xilinks ise, so that we can directly work with fixed point numbers
Thank you,

For fixed point support, use the package 'fixed_pkg'. If not included already with ISE, then Google for 'fixed pkg vhdl package'. The source code is freely available, and can be added to your project if ISE doesn't have it already. This package is synthesizable.

Kevin Jennings

 

[Y.SAI SARASWATHI]

Thank you every one,
I require one more clarification regarding usage of those fixed point numbers.
If I wish to implement multiplier and accumulator logic like I have mentioned in the first post where all coefficients(a1,a2,.....) are fixed point numbers. Can I simply write code using FOR LOOP and multiplication operator(*) or there is another procedure.
NOTE: I have used sfixed datatype (i,e a1,a2,.... are stored as array of sfixed type(Register))

 

[TrickyDicky]

You could use a for loop, but remember that a for loop unrolls in hardware, to give either parrallel or serial hardware, depending on the context of the code.

Much better to draw out the circuit diragram BEFORE you write any VHDL.