VHDL Syntax error in Modelsim simulator

Hi Frnds,

Below vhdl statment is giving syntax error in modelsim simulator,Could you correct this error.

f0 <= ((seq_pat(0) xnor Rx_data(55))+(seq_pat(1) xnor Rx_data(54))+ (seq_pat(2) xnor Rx_data(53))+(seq_pat(3) xnor Rx_data(52)));

error:** Error: D/binary_pattern_correlator.vhd(74): No feasible entries for infix operator "+".

Thanks,
vk

error vhdl infix operator

I beleave your problem is the + operator does not understand one or two of the types coming into it and/or out of it.

Try converting all the + operator inputs to integers and back again like so:

f0 <= conv_std_logic_vector(conv_integer(seq_pat(0) xnor Rx_data(55))+conv_integer(seq_pat(1) xnor Rx_data(54))+ conv_integer(seq_pat(2) xnor Rx_data(53))+conv_integer(seq_pat(3) xnor Rx_data(52)),f0'length);

Note: I have assuemed that f0 is a std_logic_vector and you are using these libaries.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
If you will need to use different conversion functions.

Hope this helps.

PS: what are you actualy trying to do here?

syntax error in vhdl

Thanks for your kind response.

I am trying to find correlation of two sequences ,for that i am using one IEEE

derived fromula..

Yeah "fo" is std logic vector,So i am using the libraries you mentioned.

I will try with your solution and get back to you...

Thanks,
venkat k

Re: VHDL Syntax error

You must mention the ARITH libraries for + to wrk out in your code.

Re: VHDL Syntax error

Hi Frnd,

The problem is sloved.

Thanks.
vk

VHDL Syntax error

Hi frnd,

Here is one small issue while simulating below code

signal parallel_data:std_logic_vector(55 downto 0):= "00000000000000000000000000000000000000000000000000000000";
process( clock,reset)
variable count: integer range 0 to 56 := 0;
begin
if clock'event and clock = '1' then
if reset = '0' then
count := 0;
parallel_data <= "00000000000000000000000000000000000000000000000000000000";
parallel_data_out <= "00000000000000000000000000000000000000000000000000000000";
Device_en <= '0';
else
if(count <= 55) then
parallel_data(count-1) <= serial_data_in;
count := count +1


In the above code simulator is strucked at this line

parallel_data(count-1) <= serial_data_in;

serial_data_in is single bit signal


and giving error like below

# Fatal error in Process line__17 at D:/Vlsiprojects/Student_projects/Sunitha_pj/Code_development/frame_synchronizer/Vhdl_Ver/serial_2_parallel.vhd line 28

28 th line is

parallel_data(count-1) <= serial_data_in;


Please give me correct syntax for this..

Thanks,
vk

Re: VHDL Syntax error


are any other set of conditions you rae checking in the else conditions ?

please check the syntax

elsif

instead of else
if (...... .... . .. )


please do let me know the rest of the code.

Re: VHDL Syntax error

Try this:

Re: VHDL Syntax error

Hi,

I Sloved this problem.

in this code bug is here..

parallel_data(count-1) <= serial_data_in;

Here count is range from 0 to 55

so i am doing count-1 operation that means 0 -1 = -1

-1 is not in the range of count.SO that is why simulator is strucked at this point..

Thanks,
vk

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