shaiko
Advanced Member level 5
When adding std_logic_vector a logic '1' - I write:
some_std_logic_vector <= some_std_logic_vector + '1'
However,
When using the standart unsigned type , we should write :
some_unsigned <= some_unsigned + 1 -- we musn't use the inverted commas
What is the reason ?
some_std_logic_vector <= some_std_logic_vector + '1'
However,
When using the standart unsigned type , we should write :
some_unsigned <= some_unsigned + 1 -- we musn't use the inverted commas
What is the reason ?