VHDL SPI interface two FPGA

[ayanmosh]

Hello,
This forum has been really helpful, I have gone really far into my project but I have two small little problems.
Details about my project:

I need to use SPI to connect two FPGA's (BASYS 2 SPARTAN 3e). Everything works except I have two problems:

Here is a youtube video of my problem:

https://www.youtube.com/watch?v=NMU0-LgUMZc

If you see in this video, when I press btn1, it sends data to the slave, but the problem is that I need to "catch" it on the right time, in order to get a mirror image of the master.

Here is my master code:

---

Code VHDL - [expand]
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library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
 
entity fpga is
port(
clk : in std_logic;
btn : in std_logic;
sclk : out std_logic;
mosi : out std_logic;
ss : out std_logic;
input : in std_logic_vector (7 downto 0);
seg : out std_logic_vector (6 downto 0);
an : out std_logic_vector (3 downto 0)
);
end fpga;
 
architecture anderson of fpga is
 
component decoder
port(
input : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0)
);
end component;
 
signal counter : std_logic_vector(18 downto 0);
signal sel : std_logic;
signal an1, an2 : std_logic_vector(6 downto 0);
type state_type is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal next_state, current_state: state_type; 
signal count_reg, next_count : std_logic_vector (7 downto 0); 
signal data: std_logic_vector(7 downto 0);
signal input_read: std_logic_vector(7 downto 0);
 
 
begin 
 
seg_one : decoder
port map(
input => input(7 downto 4),
seg => an1
); 
seg_two : decoder
port map(
input => input(3 downto 0),
seg => an2
);
sclk <= clk after 50 ns;
 
process (btn)
begin 
 
case current_state is 
 
when s0 => -- S0 no data sent
if btn = '1' then 
    
ss<='0';
mosi<='0';
data <= input;
next_state <= s1;
else
next_state<=s0;
end if;
 
when s1 => mosi <= data(0); 
next_state <= s2;
 
when s2 => mosi <= data(1); 
next_state <= s3; 
 
when s3 => mosi <= data(2); 
next_state <= s4; 
 
when s4 => mosi <= data(3); 
next_state <= s5;
 
when s5 => mosi <= data(4); 
next_state <= s6;
 
when s6 => mosi <= data(5); 
next_state <= s7;
 
when s7 => mosi <= data(6); 
next_state <= s8;
 
when s8 => mosi <= data(7); 
next_state <= s0; 
 
when others => mosi <='0';
 
end case;
 
end process;
 
process (clk)
begin
if falling_edge (clk)
then 
current_state<= next_state;
 
end if;
end process;
 
-- Combinational Logic
 
sel <= counter(16);
process(sel)
begin
case sel is
when '0' => an <= "1110"; seg <= an2;
when '1' => an <= "1101"; seg <= an1;
when others => an <= "1111";
end case;
end process;
 
process(clk)
begin 
 
    
if rising_edge(clk) then
counter <= counter + 1;
end if;
end process; 
 
 
end;

---

And here is my slave code

---

Code VHDL - [expand]
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library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fpga is
port(
clk : in std_logic;
mosi : in std_logic;
ss : in std_logic;
seg : out std_logic_vector (6 downto 0);
an : out std_logic_vector (3 downto 0)
);
end fpga;
architecture anderson of fpga is
 
component decoder
port(
input : in STD_LOGIC_VECTOR(3 downto 0);
seg : out STD_LOGIC_VECTOR(6 downto 0));
end component;
 
 
 
signal counter : std_logic_vector(25 downto 0):=(others => '0');
signal an1 : std_logic_vector(3 downto 0); 
signal an2 : std_logic_vector(3 downto 0);
type state_type is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
signal next_state, current_state: state_type; 
signal count_reg, next_count : std_logic_vector (7 downto 0);
signal data: std_logic_vector(7 downto 0);
signal data1: std_logic_vector(3 downto 0); 
signal data2: std_logic_vector(3 downto 0);
signal seg1 : std_logic_vector(6 downto 0);
signal seg2 : std_logic_vector(6 downto 0);
signal data_reg : std_logic_vector(7 downto 0):="11111111";
 
begin 
Label1 : decoder
port map(
input => data(7 downto 4),
seg => seg1
); 
Label2 : decoder
port map(
input => data(3 downto 0),
seg => seg2
);
 
 
 
 
 
process (ss)
begin 
 
case current_state is 
 
when s0 => 
if (ss='1') then
next_state <=s1;
else next_state <=s0;
end if;
when s1 => data_reg(0) <= mosi; 
next_state <= s2;
 
 
when s2 => data_reg(1) <= mosi; 
next_state <= s3; 
 
 
when s3 => data_reg(2) <= mosi; 
next_state <= s4; 
 
 
when s4 => data_reg(3) <= mosi; 
next_state <= s5;
 
 
when s5 => data_reg(4) <= mosi; 
next_state <= s6;
 
when s6 => data_reg(5) <= mosi; 
next_state <= s7;
 
when s7 => data_reg(6) <= mosi; 
next_state <= s8;
 
when s8 => data_reg(7) <= mosi; 
 
next_state <= s0;
 
end case;
end process;
data <= data_reg(7 downto 0);
data1 <= data(7 downto 4);
data2 <= data(3 downto 0);
 
 
 
-- Combinational Logic
 
 
 
process (counter(15))--- flips the an's so they are both on
begin
case counter(15) is
when '0' => seg <= seg2; an <= "1110";--digit0
when '1' => seg <= seg1; an <= "1101";--digit1
when others => seg <= "1111111"; an <= "1111"; --uhoh
end case;
end process; --------------------------------------------
 
 
process(clk) --- clock increases the timer
begin
if (rising_edge(clk)) then
 
counter <= counter + '1';
current_state <= next_state;
 
end if;
end process;
 
 
end;

---

The main problem that I am trying to solve is that when I press the button on the master fpga, the display on the slave should match the master's, but this is only working if I "catch" the right signal.

I think my problem is that I don't know how to use the sclk signal. Since I am not even using it on the slave....
Any help please?

 

[lucbra]

if you don't use the sclk, your slave is not in sync with your master