VHDL Simulation warning / Error

[sathishkas]

Hi,

I have written a simple D Flip-flop code and a corresponding test bench in VHDL code. While I compiled I didnt get any warnings/errors. But when I was running VHDL Simulation with NC-Sim I encountered the following error. I need to dump out the waveform and check the output. Should I specify any time scale value in the RTL file. If so, how to specify the timescale value?

Run Command : irun dff.vhd tb_dff.vhd -gui &

Error :
irun: 12.10-s004: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
irun: *E,VHDLTP: VHDL files are being compiled. The utility does not automatically calculate top-level VHDL design units.


Can anyone tell me how to resolve the problem.

 

[imbichie]

try this one

irun -gui -f file_list -top tb_dff -access +rwc

Here the "file_list" is a file which contains the filename with path of all files which are needs to be compiled.
after " -top " you need to put the testbench entity name, i hope it is tb_dff, if not please change it and run it

 

[sathishkas]

Thanks for your reply.

Now it's working fine. But When I simulate it, all my inputs/outputs are getting a value of 'U' (Undefined Value) moreover, I am not getting any waveform.

Could you please tell me what are the things I should do to get the correct value while doing the simulation.

Thanks,
Sathish

 

[imbichie]

check your reset in the module, also need to confirm you are driving all the signals well